參數(shù)資料
型號(hào)： KS8695X-EVAL
廠(chǎng)商： Micrel Inc
文件頁(yè)數(shù)： 32/39頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL EXPERIMENT KS8695X
標(biāo)準(zhǔn)包裝： 1
相關(guān)產(chǎn)品： KS8695X-ND - IC SWITCH 10/100 5PORT 208PQFP
其它名稱(chēng)： 576-1005
KS8695X
Micrel
M9999-102604
38
October 2004
Symbol
Parameter
Registers
RBiTPACC
Programmable bank i access time
0x4010, 0x4014
RBiTPA
Programmable bank i page address access time
0x4010, 0x4014
Table 9. Static Memory Timing Parameters
Symbol
Parameter
Min
Typ
Max
Units
SDRAM
Signals Rise Time
SDR
Clock rise time
4.2
4.0
4.8
ns
SDR
Address rise time
3.8
4.4
4.8
ns
SDR
Bank select rise time
3.6
4.2
4.4
ns
SDR
Data rise time
ns
SDR
Chip select rise time
3.0
3.7
ns
SDR
RAS rise time
3.4
3.6
3.8
ns
SDR
CAS rise time
3.0
3.5
3.4
ns
SDR
WE rise time
3.0
3.8
ns
SDR
DQM rise time
3.2
3.5
ns
SDRAM Signal Fall Time
SDR
Clock fall time
5.0
6.0
6.4
ns
SDR
Address fall time
4.4
5.4
5.5
ns
SDR
Bank select fall time
5.2
5.5
6.0
ns
SDR
Data fall time
ns
SDR
Chip select fall time
3.6
4.2
ns
SDR
RAS fall time
3.8
4.4
ns
SDR
CAS fall time
4.0
3.8
4.8
ns
SDR
WE fall time
4.2
4.4
4.5
ns
SDR
DQM fall time
4.0
4.4
ns
SDRAM Timing Specifications
t01
Clock-to-chip select output delay
0.7
0.9
ns
t11
Clock-to-chip select hold time
0.7
0.6
ns
t02
Clock-to-address high-to-low
1.2
1.6
1.7
ns
t12
Clock-to-address low-to-high
1.3
1.5
1.6
ns
t03
Clock-to-bank select high-to-low
1.9
1.8
1.9
ns
t13
Clock-to-bank select low-to-high
1.3
1.5
ns
t04
Clock-to-RAS output delay
1.1
1.5
ns
t14
Clock-to-RAS hold time
1.1
0.9
1.3
ns
t05
Clock-to-CAS output delay
1.3
1.1
1.5
ns
t15
Clock-to-CAS hold time
0.9
1.1
ns
t06
Clock-to-WE output delay
1.1
1.3
1.5
ns
t16
Clock-to-WE hold time
0.8
1.1
1.3
ns
t07
Clock-to-DQM output delay
0.7
1.1
ns
t17
Clock-to-DQM hold time
0.8
1.4
1.3
ns
t08
Clock-to-data output delay
0.4
0.6
0.8
ns
t18
Clock-to-data hold time
0.1
0.4
0.6
ns
Table 8. SDRAM Interface Timing
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