參數(shù)資料
型號(hào)： KS16114
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 9600/14400 bps FAX MODEM
中文描述： 14400分之9600基點(diǎn)傳真調(diào)制解調(diào)器
文件頁(yè)數(shù)： 24/69頁(yè)
文件大小： 513K
代理商： KS16114
KS16112/4
9600/14400 bps FAX MODEM
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24
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DATM
Data Mode
0C : 5 ( - )
Status bit DATM is set by the modem to indicate that the transmitter or receiver is in data mode. Data
mode implies that the modem is in a state where user data may be transmitted or received.
DBFR
Transmit/Receive Data Buffer
10 : 0 - 7 ( - )
When the modem is configured in parallel data mode ( PDME is set ), the host microprocessor reads parallel
received data from DBFR or writes parallel transmit data into DBFR. DBFR data is transmitted bit 0 first.
Transmission and reception of data is synchronized by polling the BDA2 status bit or by IRQ interrupts
( see INTE2 and INTA2 bit descriptions ).
When CRCE and EOHF are both set, the received frame is erroneous. If CRCE is reset and EOHF is set
the received frame is correct. CRCE becomes valid immediately before EOHF is set.
The host informs the modem to implement a configuration change by setting the CSET bit. The host sets
the CSET bit after writing a configuration code into the CONFIG bits ( register 6:0-7 ).
The CSET bit is reset by the modem after the configuration change has been completed.
CRCE
Cyclic Redundancy Check Error
09 : 1 ( - )
CSET
Configuration Setup
1F : 0 ( 0 )
CTSB
Clear to Send Bit
0F : 1 ( - )
When CTSB is set the modem has completed the training sequence transmission and any data present at
TXDI ( if PDME is reset ) or DBFR ( if PDME is set ) will be transmitted. CTSB parallels the operation of
the CTS output pin.
When CRAM2 is set, ADR2 addresses coefficient RAM and when CRAM2 is reset, ADR2 addresses data
RAM. This bit must be set according to the desired RAM address.
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