參數(shù)資料
型號(hào)： KS16114
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 9600/14400 bps FAX MODEM
中文描述： 14400分之9600基點(diǎn)傳真調(diào)制解調(diào)器
文件頁(yè)數(shù)： 22/69頁(yè)
文件大?。?/td> 513K
代理商： KS16114
KS16112/4
9600/14400 bps FAX MODEM
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22
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When AHEOF is set while in HDLC transmit mode, the modem automatically generates and transmits the
FCS ( frame check sequence ) and at least one closing flag upon detecting an underrun condition in the
transmission of data. AHEOF is valid only when the modem is configured for HDLC mode ( HDLCE is set ).
Buffer Data Available No.2
1E : 0 ( - )
When BDA1 has been set by the modem, the modem has either written or read buffer data to/from the
YDL1 register. The setting of the BDA1 bit can be setup to cause an IRQ interrupt ( see INTE1 and
INTA1 bit descriptions ). When the host microprocessor reads or writes the YDL1 register, the modem
automatically resets the BDA1 bit.
BDA 1
Buffer Data Available No.1
1E : 3 ( - )
When BDA2 has been set by the modem and the modem is in parallel data mode ( PDME is set ), with
or without HDLC enabled, transmit data has been read from DBFR by the modem ( transmit mode ) or
received data has been written by the modem into DBFR ( receive mode ). When the modem is in serial
mode ( PDME is reset ), the modem sets BDA2 whenever data has been read from or written into YDL2.
The setting of the BDA2 bit can be setup to cause an IRQ interrupt ( see INTE2 and INTA2 bit descrip -
tions ). When the host microprocessor reads or writes the YDL2/DBFR register, the modem automatically
resets the BDA2 bit.
BRT 1
Baud Rate 1
05 : 2 ( 1 )
When BRT1 is set, RAM access for ADR1 takes place at the baud rate ( the baud rate depends on the se -
lected configuration ), otherwise it occurs at the sample rate ( 9600Hz ). This bit must be zero in FSK, Tone
or DTMF receive modes.
BRT 2
Baud Rate 2
15 : 2 ( 0 )
When BRT2 is set RAM access for ADR2 takes place at the baud rate ( the baud rate depends on the se -
lected configuration ). Otherwise it occurs at the sample rate ( 9600Hz ). This bit must be zero in FSK, Tone
or DTMF receive modes.
CASC
Select 12th Order Filter Cascade
08 : 4 ( 0 )
When CASC is set, the tone detectors are cascaded to form one 12th order filter ( TD3 is the output status
bit for the 12th order filter cascade ). When CASC is reset, the three tone detectors operate as three parallel
independent 4th order filters. The 12th order mode is only valid in the FSK , FSK and DTMF receiver
modes when RTS is off and RTSB is reset.
AHEOF
Automatic HDLC End of Frame
15 : 5 ( 0 )
BDA 2
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