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參數(shù)資料
| 型號： | KMM350S823BT1 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 8M x 72 SDRAM DIMM(8M x 72同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 8米× 72 SDRAM的內(nèi)存（8米× 72同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 180K |
| 代理商： | KMM350S823BT1 |
REV. 4 Aug. 1998
Preliminary
KMM350S823BT1
SDRAM MODULE
PIN CONFIGURATION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.
A0 ~ A11
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA8
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7
Data input/output mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
REGE
Register enable
The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and con-
trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to V
CC
through 10K ohm
Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-
istered mode.
DQ0 ~ 63
Data input/output
Data inputs/outputs are multiplexed on the same pins.
CB0 ~ 7
Check bit
Check bits for ECC.
WP
Write protection
WP pin is connected to V
SS
through 47K
Resistor.
When WP is "high", EEPROM Programming will be inhibited and the entire memory will
be write-protected.
V
DD
/V
SS
Power supply/ground
Power and ground for the input buffers and the core logic.
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