參數(shù)資料
型號(hào)： KMM350S823BT1
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 8M x 72 SDRAM DIMM(8M x 72同步動(dòng)態(tài)RAM模塊)
中文描述： 8米× 72 SDRAM的內(nèi)存（8米× 72同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 13/14頁(yè)
文件大?。?/td> 180K
代理商： KMM350S823BT1
SERIAL PRESENCE DETECT
SDRAM MODULE
Byte #
Function described
Function Supported
Hex value
Note
-8
H
-L
-8
-H
-L
0
# of bytes written into serial memory at module manufacturer
128bytes
80h
1
Total # of bytes of SPD memory device
256bytes (2K-bit)
08h
2
Fundamental memory type
SDRAM
04h
3
# of row address on this assembly
12
0Ch
1
4
# of column address on this assembly
9
09h
1
5
# of module Rows on this assembly
1 Row
01h
6
Data width of this assembly
72 bits
48h
7
...... Data width of this assembly
-
00h
8
Voltage interface standard of this assembly
LVTTL
01h
9
SDRAM cycle time from clock @CAS latency of 3
8ns
10ns
10ns
80h
A0h
A0h
2
10
SDRAM access time from clock @CAS latency of 3
6ns
6ns
6ns
60h
60h
60h
2
11
DIMM configuraion type
ECC
02h
12
Refresh rate & type
15.625us, support self refresh
80h
13
Primary SDRAM width
x8
08h
14
Error checking SDRAM width
x8
08h
15
Minimum clock dealy for back-to-back random column address
t
CCD
= 1CLK
01h
16
SDRAM device attributes : Burst lengths supported
1, 2, 4, 8 & full page
8Fh
17
SDRAM device attributes : # of banks on SDRAM device
4 banks
04h
18
SDRAM device attributes : CAS latency
2 & 3
06h
19
SDRAM device attributes : CS latency
0 CLK
01h
20
SDRAM device attributes : Write latency
0 CLK
01h
21
SDRAM module attributes
Registered/Buffered DQM,
address & control inputs
1Bh
22
SDRAM device attributes : General
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
0Eh
23
SDRAM cycle time @CAS latency of 2
12ns
10ns
12ns
C0h
A0h
C0h
2
24
SDRAM access time @CAS latency of 2
6ns
6ns
7ns
60h
60h
70h
2
25
SDRAM cycle time @CAS latency of 1
-
-
-
00h
00h
00h
2
26
SDRAM access time @CAS latency of 1
-
-
-
00h
00h
00h
2
27
Minimum row precharge time (=t
RP
)
20ns
20ns
20ns
14h
14h
14h
28
Minimum row active to row active delay (t
RRD
)
16ns
20ns
20ns
10h
14h
14h
29
Minimum RAS to CAS delay (=t
RCD
)
20ns
20ns
20ns
14h
14h
14h
30
Minimum activate precharge time (=t
RAS
)
48ns
50ns
50ns
30h
32h
32h
31
Module Row density
1 Row of 64MB
10h
32
Command and Address signal input setup time
2ns
20h
33
Command and Address signal input hold time
1ns
10h
34
Data signal input setup time
2ns
20h
KMM350S823BT1-G8/GH/GL(1.0ver)
Organization : 8MX72
Composition : 8MX8 *9
Used component part # : KM48S8030BT-G8/GH/GL
# of banks in module : 1 Row
# of banks in component : 4 banks
Feature : 1,500 mil height & double sided component
Refresh : 4K/64ms
Contents
:
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