參數(shù)資料
型號(hào)： KM29W16000ATS
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 2M x 8 Bit NAND Flash Memory(2M x 8位 NAND閃速存儲(chǔ)器)
中文描述： 200萬(wàn)× 8位NAND閃存（2米× 8位的NAND閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 5/21頁(yè)
文件大?。?/td> 250K
代理商： KM29W16000ATS
KM29W16000ATS
FLASH MEMORY
5
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the path activation for address and input data to the internal address/data register.
Addresses are latched on the rising edge of WE with ALE high, and input data is latched when ALE is low.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling ed ge
of RE which also increments the internal column address counter by one.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to outputs data during read operations. The I/O pins float to high -z
when the chip is deselected or the outputs are disabled.
Write Protect (WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and return to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is
deselected or outputs are disabled.
Power Line(V
CC
& V
CCQ
)
The V
CCQ
is the power supply for I/O interface logic. It is electrically isolated from main power line(V
CC
=2.7~5.5V) for supporting 5V
tolerant I/O with 5V power supply at V
CCQ
.
相關(guān)PDF資料
PDF描述
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