- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374353 > KM29W16000AIT (SAMSUNG SEMICONDUCTOR CO. LTD.) 2M x 8 Bit NAND Flash Memory(2M x 8位 NAND閃速存儲器) PDF資料下載
參數(shù)資料
| 型號： | KM29W16000AIT |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2M x 8 Bit NAND Flash Memory(2M x 8位 NAND閃速存儲器) |
| 中文描述： | 200萬× 8位NAND閃存（2米× 8位的NAND閃速存儲器） |
| 文件頁數(shù)： | 4/23頁 |
| 文件大?。?/td> | 266K |
| 代理商： | KM29W16000AIT |
KM29W16000AT, KM29W16000AIT
FLASH MEMORY
4
PRODUCT INTRODUCTION
The KM29W16000A is a 16.5Mbit(17,301,504 bit) memory organized as 8192 rows by 264 columns. Spare eight columns are
located from column address of 256 to 263. A 264-byte data register is connected to memory cell arrays accommodating data trans-
fer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells
that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the
pages formed by one NAND structures, totaling 264 NAND structures of 16 cells. The array organization is shown in Figure 2. The
program and read operations are executed on a page basis, while the erase operation is executed on block basis. The memory array
consists of 512 separately or grouped erasable 4K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
KM29W16000A.
16
The KM29W16000A has addresses multiplexed into 8 I/O
′
s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written throug h
I/O`s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block
address loading. The 2M byte physical space requires 21 addresses, thereby requiring three cycles for byte-level addressing : co l-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address
cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the KM29W16000A.
Table 1. COMMAND SETS
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Sequential Data Input
80h
-
Read 1
00h
-
Read 2
50h
-
Read ID
90h
-
Reset
FFh
-
O
Page Program
10h
-
Block Erase
60h
D0h
Read Status
70h
-
O
相關PDF資料 |
PDF描述 |
|---|---|
| KM29W16000AT | 2M x 8 Bit NAND Flash Memory(2M x 8位 NAND閃速存儲器) |
| KM29W16000ATS | 2M x 8 Bit NAND Flash Memory(2M x 8位 NAND閃速存儲器) |
| KM29W32000AIT | 4M x 8 Bit NAND Flash Memory(4M x 8 位 NAND閃速存儲器) |
| KM29W32000AT | 4M x 8 Bit NAND Flash Memory(4M x 8 位 NAND閃速存儲器) |
| KM29W32000AK1 | 4M x 8 Bit NAND Flash Memory(4M x 8 位 NAND閃速存儲器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| KM2M COMBO-L | 制造商:Micro-Star International 功能描述:KM266 UATX AMD 266FSB DDR - Bulk |
| KM2M806XT | 制造商:Kontron 功能描述:M2M DEPLOYMENT UNIT FOR APPLICATIONS IN HARSH ENVIRONMENTS - Boxed Product (Development Kits) |
| KM2M810-01 | 制造商:Kontron 功能描述:FRI 2.0 DEVELOPMENT KIT WITHOUT THE ERICSSON MODEM - Boxed Product (Development Kits) |
| KM2M810-02 | 制造商:Kontron 功能描述:FRI 2.0 DEVELOPMENT KIT WITH ERICSSON MODEM - Boxed Product (Development Kits) |
| KM2M810-08 | 制造商:Kontron 功能描述:FRI 2.0 DEV KIT WITH ERICSSON MODEM, PTCRB CERTIFIED - Boxed Product (Development Kits) |
發(fā)布緊急采購，3分鐘左右您將得到回復。