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參數(shù)資料
| 型號： | KM29W16000AIT |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2M x 8 Bit NAND Flash Memory(2M x 8位 NAND閃速存儲器) |
| 中文描述： | 200萬× 8位NAND閃存（2米× 8位的NAND閃速存儲器） |
| 文件頁數(shù)： | 21/23頁 |
| 文件大?。?/td> | 266K |
| 代理商： | KM29W16000AIT |
KM29W16000AT, KM29W16000AIT
FLASH MEMORY
21
Figure 9. Read ID Operation
READ ID
The device contains a product identification mode, initiated by writing 90H to the command register, followed by an address inpu t of
00H. Two read cycles sequentially output the manufacture code(ECH), and the device code (Note*) respectively. The command reg-
ister remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
CE
CLE
I/O
0 ~ 7
ALE
RE
WE
90H
Address. 1 cycle
Dout(ECH)
Dout(Note*)
A
0
~ A
7
:"0"
Maker code
Device code
t
CR
t
AR1
t
REA
Note* KM29V16000 : EAH
KM29N16000 : 64H
KM29W16000 : EAH
Figure 10. RESET Operation
RESET
The device offers a reset feature, executed by writing FFH to the command register. When the device is in Busy state during rand om
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0H when WP is high. Refer to table 3 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/ B pin transitions to low for tRST
after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 10 below.
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
FFH
I/O
0 ~ 7
R/B
Table3. Device Status
t
RST
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