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Functional Description and Application Information
Serial Peripheral Interface (S12SPIV4)
MM912F634
Freescale Semiconductor
325
4.38.4.3
Transmission Formats
During a SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial
clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection
of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a
master SPI device, the slave select line can be used to indicate multiple-master bus contention.
Figure 102. Master/Slave Transfer Block Diagram
4.38.4.3.1
Clock Phase and Polarity Controls
Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity.
The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format.
The CPHA clock phase control bit selects one of two fundamentally different transmission formats.
Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the
phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having
different requirements.
4.38.4.3.2
CPHA = 0 Transfer Format
The first edge on the SCK line is used to clock the first data bit of the slave into the master, and the first data bit of the master
into the slave. In some peripherals, the first bit of the slave’s data is available at the slave’s data out pin as soon as the slave is
selected. In this format, the first SCK edge is issued a half cycle after SS has become low.
A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value previously latched
from the serial data input pin is shifted into the LSB or MSB of the shift register, depending on LSBFE bit.
After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial
input pin on the slave. This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered
edges and shifted on even numbered edges.
Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer, and is transferred to the
parallel SPI data register after the last bit is shifted in.
After the 16th (last) SCK edge:
Data that was previously in the master SPI data register should now be in the slave data register, and the data that was
in the slave data register should be in the master.
The SPIF flag in the SPI status register is set, indicating that the transfer is complete.
SHIFT REGISTER
BAUD RATE
GENERATOR
MASTER SPI
SLAVE SPI
MOSI
MISO
SCK
SS
VDD