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參數(shù)資料
| 型號(hào)： | KIT912F634EVME |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 181/339頁(yè) |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR MM912F634 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | MCU |
| 適用于相關(guān)產(chǎn)品： | MM912F634 |
| 所含物品： | 板，線纜，CD |
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Functional Description and Application Information
Real Time Interrupt (S12SRTIV1)
MM912F634
Freescale Semiconductor
261
4.34.7
Functional Description
The S12SCRG generates a real time interrupt when the selected interrupt time period elapses. The interrupt period is selected
by the RTICTL and RTICNT register (see Table 340). RTI interrupts are locally disabled by setting the RTIE bit to zero. The real
time interrupt flag (RTIF) is set to 1 when a time-out occurs, and is cleared to 0 by writing a 1 to the RTIF bit.
The RTI continues to run during Stop mode if the RTIRSTP bit is set. This feature can be used for periodic wake-up from Stop if
the RTI interrupt is enabled.
Also the RTI continues to run during Wait mode if the RTISWAI bit is cleared. This feature can be used for periodic wake-up from
Wait if the RTI interrupt is enabled.
If the RTIFRZ bit of the RTICTL register is set the RTI timer is frozen during BDM active mode.
Modifying the RTI registers that way that the Frequency Divider Rate changes from OFF condition to any time-out period
immediately starts the RTI counter with a full period. When the RTIRT bits are written to modify the current time-out period while
the RTI counter is running the new value will be loaded into the Prescaler at the end of the current time-out period. Also when
the RTICNT register gets modified while the RTI counter is running the new RTICNT values will be loaded into the Modulus Down
Counter at the end of the current RTI period. Hence, frequent modification of the RTIRT bits and RTICNT register faster than the
actual selected time-out period will result in ignored values and only the value available at current time-out will be loaded for the
next time-out period.
The RTI Modulus Down Counter and Prescaler are clocked by the internal reference clock other than the RTI registers which are
clocked with the internal bus clock. Both clocks are asynchronous and information exchange between these two clock domains
is synchronized. Please refer to the SoC Guide for more information regarding these clocks and see 4.34.7.1, “RTI register write
protection rules“ and 4.34.7.2, “Modification of Prescaler rate (RTIRT bits)“ and 4.34.7.3, “Modification of Modulus Down Counter
rate (RTICNT register)“ for RTI register access rules.
4.34.7.1
RTI register write protection rules
As mentioned, the RTI registers and RTI counter are running on two different asynchronous clock domains. Therefore there is a
synchronization delay when modifying the registers with regard to time-out period until the modification takes affect. The
synchronization delay is typically three clock cycles on the counter clock domain and two clock cycles on the register clock
domain. This means that it takes three cycles in the clock domain of the RTI counter (internal reference clock) to receive the
modified time-out values and two cycles in the RTI register clock domain (bus clock) to receive the time-out flag from the counter
in the register. Also a write access to the RTICNT register locks this register and a write access to the RTICTL register locks the
RTIRT bits against further write accesses for three internal reference clock cycles plus two bus clock cycles after the write access
occurred, which is due to synchronization. Therefore modifying the RTICNT register or RTIRT bits faster than they are
synchronized results in ignored values.
In general it should be avoided to access both registers in a single word access if only one of the registers should be modified.
4.34.7.2
Modification of Prescaler rate (RTIRT bits)
Applications which modify the Frequency Divider Rate by modifying the RTIRT bits (Prescaler rate) in the RTICTL register should
follow below recommendations.
1111 1111 (
256)
OFF
256x1
256x16
256x256
Note:
188. Denotes the default value out of reset.This value disable the RTI.
Table 340. RTI Frequency Divide Rates (continued)
RTICNT[7:0]
RTIRT[1:0] =
00
(OFF)
01
(1)
10
(16)
11
(256)
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