SUPPLEMENTAL APPLICATION NOTES Fi" />
參數(shù)資料
型號： KIT33989DWEVB
廠商： Freescale Semiconductor
文件頁數(shù)： 41/72頁
文件大小： 0K
描述： KIT EVAL 33989DW HS SBC
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，CAN 控制器
嵌入式： 是，MCU，8 位
已用 IC / 零件： MC33989
主要屬性： CAN 2.0 系統(tǒng)基礎(chǔ)芯片（SBC），SPI 接口，2 低壓降穩(wěn)壓器
次要屬性： 故障檢測，睡眠和待機模式
已供物品： 板，CD
相關(guān)產(chǎn)品： MC33989DWR2CT-ND - IC SYSTEM BASE W/CAN 28-SOIC
MC33989DWR2TR-ND - IC SYSTEM BASE W/CAN 28-SOIC
MC33989DW-ND - IC SYSTEM BASE W/CAN 28-SOIC
Analog Integrated Circuit Device Data
46
Freescale Semiconductor
33989
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
Figure 24. Power Up and VDD1 Going Low with Stop Mode as Default Low Power Mode Selected
Power Up and VDD1 Going Low with Sleep Mode as Default Low Power Mode Selected
The first part of the graph is the same as the previous figure. If VDD1 is pulled below the VDD1 undervoltage reset (typ 4.6 V)
for instance by an overcurrent or short-circuit (ex short to 4.0 V), and if the low power mode previously selected was sleep mode
and if the BATFAIL flag has been cleared, the SBC enters reset mode for a time period of 100 ms. The pin WD stays high, but
the high level (VOH) follows the VDD1 level.The reset and interrupt pins are low. After the 100 ms, the SBC goes into Sleep mode.
VDD1 and V2 are off (The following figure is an example where VDD1 is shorted to 4.0 V, and after 100 ms the SBC enters sleep
mode.
Figure 25. Power up and VDD1 Going Low with Sleep Mode as Default Low Power Mode Selected
WAKE-UP TIMINGS — SLEEP MODE
The paragraphs below describe the wake-up events from Sleep mode, and the sequence of the signals at the SBC level. The
wake-up time described is the time from the wake-up event to the SBC reset pin release. The wake-up time is the sum of several
timings: wake-up signal detection, VDD1 regulator start-up and decoupling capacitor charge, and reset time. At the end of the
reset time, the reset pin goes from low to high and the MCU is ready to start software operations.
SBC in Normal request
mode
SBC in Normal
mode
SBC in Reset
mode
SBC in Normal
Request mode
350 ms
SBC in
RESET
mode
350 ms
VDD1
SPI (CS)
INT
WD
RST
Reset every 350 ms
No problem on
Watchdog period
Write Watchdog
each X ms
SBC in R e s e t
m o de
(B A T F A IL fla g
mu st b e c le a re d )
SB C in Sle e p m o d e
100 ms
S B C in N o rm a l re qu es t
mo d e
SBC in N o rm a l
mo d e
SBC in
R ESE T
mo d e
350 ms
VDD1
SPI (CS)
INT
WD
RST
Reset every 350 ms
Write Watchdog
each X ms
No problem on
Watchdog period
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