LOGIC COMMANDS AND REGISTERS Figure 16. Sim" />
參數(shù)資料
型號： KIT33989DWEVB
廠商： Freescale Semiconductor
文件頁數(shù)： 24/72頁
文件大?。?/td> 0K
描述： KIT EVAL 33989DW HS SBC
標(biāo)準包裝： 1
主要目的： 接口，CAN 控制器
嵌入式： 是，MCU，8 位
已用 IC / 零件： MC33989
主要屬性： CAN 2.0 系統(tǒng)基礎(chǔ)芯片（SBC），SPI 接口，2 低壓降穩(wěn)壓器
次要屬性： 故障檢測，睡眠和待機模式
已供物品： 板，CD
相關(guān)產(chǎn)品： MC33989DWR2CT-ND - IC SYSTEM BASE W/CAN 28-SOIC
MC33989DWR2TR-ND - IC SYSTEM BASE W/CAN 28-SOIC
MC33989DW-ND - IC SYSTEM BASE W/CAN 28-SOIC
Analog Integrated Circuit Device Data
30
Freescale Semiconductor
33989
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Figure 16. Simplified State Machine in Debug Modes
LOGIC COMMANDS AND REGISTERS
SPI INTERFACE AND REGISTER DESCRIPTION
Table 7 illustrates a register, an 8-bit SPI. The first three bits are used to identify the internal SBC register address. Bit four is
a read/write bit. The last four bits are Data Send from MCU to SBC, or read back from SBC to MCU.
There is no significance during write operation state of MISO.
During read operation only the final four bits of MISO have a meaning (content of the accessed register).
The following tables describe the SPI register list, and register bit meaning.
Registers reset value is also described along with the reset condition. Reset condition is the condition causing the bit to be set
at the reset value.
Read operation: R/W Bit = 0
Write operation: R/W Bit = 1
Possible reset conditions include:
Table 7. Data Format Description
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
A2
A1
A0
R/W
D3
D2
D1
D0
SP
I:
S
tan
d
-by
&
WD
:T
rigger
Wake-up
Normal Request
Stand-by Debug
SP
I:Norma
lDebug
Normal
WD:
Trigg
er
Standby
SPI: Standby Debug
SP
I:
S
tand-
by
SP
I: N
orm
al D
ebu
g
Reset
Reset Counter
(3.4 ms) Expired
WD: Timeout 350 ms
&!
BA
TF
AI
LNO
S
T
O
P
&
SP
I:
Sl
e
p
SPI: Normal Debug
Normal Debug
SP
I: S
tandby
De
bug
Stop Debug
S
P
I:S
to
p
W
ake-
up
E
SPI:
S
to
p
Deb
ug
&
CS
Low
to
Hig
h
T
ran
si
tio
n
Wake-up
R
(1) If Stop mode entered, it is entered without watchdog, no matter the WDSTOP bit.
(E) Debug mode entry point (Step 5 of the Debug mode entering sequence).
(R) Represents transitions to Reset mode due to VDD1 low.
Sleep
Stop (1)
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