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| 型號(hào)： | KIT33742DWEVB |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 43/71頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | KIT FOR 33742 SBC WITH EHSCAN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，CAN 控制器 |
| 已用 IC / 零件： | MC33742 |
| 相關(guān)產(chǎn)品： | MC33742DW-ND - IC SYSTEM BASE W/LIN 28-SOIC MC33742DWR2-ND - IC SYSTEM BASE W/LIN 28-SOIC MC33742SDW-ND - IC SYSTEM BASE W/LIN 28-SOIC MC33742SDWR2-ND - IC SYSTEM BASE W/LIN 28-SOIC |
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Analog Integrated Circuit Device Data
48
Freescale Semiconductor
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
MODE CONTROL REGISTER (MCR)
Table 16. Mode Control Register
MCR
R/W
D3
D2
D1
D0
$000b
W
–
MCTR2
MCTR1
MCTR0
R
VDDTEMP
GFAIL
WDRST
Reset Value
–
0
Reset Condition (Write)(53)
–
POR, RESET
Notes
52.
BATFAIL bit cannot be set by SPI. BATFAIL is set when VSUP falls below 3.0 V.
53.
See Table 13 page 46, for definitions of reset conditions
Table 17. Mode Control Register Control Bits
MCTR
2
MCTR
1
MCTR
0
33742S Mode
Description
0
Enter/Exit Debug Mode
To enter/exit Debug Mode, refer to detailed description in Debug Mode: Hardware and
0
1
Normal
–
0
1
0
Standby
–
0
1
Stop, Watchdog OFF(54)
–
0
1
Stop, Watchdog ON(54)
–
1
0
–
1
0
1
Normal
No Watchdog running. Debug mode.
1
0
Standby
1
Stop
Notes
54.
Watchdog ON or OFF depends on RCR bit D3.
55.
Before entering Sleep mode, BATFAIL bit in MCR must be previously cleared (MCR read operation), and NOSTOP bit in RCR must be
previously set to logic [1].
Table 18. Mode Control Register Status Bits
Name
Logic
Description
BATFAIL
0
VSUP was not below VBF.
1
VSUP has been below VBF.
VDDTEMP
0
No over-temperature pre-warning.
1
Temperature pre-warning on VDD regulator (bit latched).
GFAIL
0
No failure.
1
CAN Failure or HS over-temperature or V2 low.
WDRST
0
No watchdog reset occurred.
1
Watchdog reset occurred.
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