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參數(shù)資料
| 型號(hào)： | KFN2G16Q2M-DED6 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | MuxOneNAND FLASH MEMORY |
| 中文描述： | MuxOneNAND閃存 |
| 文件頁數(shù)： | 117/124頁 |
| 文件大?。?/td> | 1550K |
| 代理商： | KFN2G16Q2M-DED6 |
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MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
FLASH MEMORY
117
From time-to-time supplemental technical information and application notes pertaining to the design and operation of the device in a
system are included in this section. Contact your Samsung Representative to determine if additional notes are available.
7.1 Methods of Determining Interrupt Status
There are two methods of determining Interrupt Status on the MuxOneNAND. Using the INT pin or monitoring the Interrupt Status
Register Bit.
The MuxOneNAND INT pin is an output pin function used to notify the Host when a command has been completed. This provides a
hardware method of signaling the completion of a program, erase, or load operation.
In its normal state, the INT pin is high if the INT polarity bit is default. Before a command is written to the command register, the INT
bit must be written to '0' so the INT pin transitions to a low state indicating start of the operation. Upon completion of the command
operation by the MuxOneNAND’s internal controller, INT returns to a high state.
INT is an open drain output allowing multiple INT outputs to be Or-tied together. INT does not float to a hi-Z condition when the chip is
deselected or when outputs are disabled. Refer to section 2.8 for additional information about INT.
INT can be implemented by tying INT to a host GPIO or by continuous polling of the Interrupt status register.
7.1.1 The INT Pin to a Host General Purpose I/O
INT can be tied to a Host GPIO to detect the rising edge of INT, signaling the end of a command operation.
This can be configured to operate either synchronously or asynchronously as shown in the diagrams below.
INT
COMMAND
7.0 TECHNICAL AND APPLICATION NOTES
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