參數(shù)資料
型號： KFN2G16Q2M-DED6
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： MuxOneNAND FLASH MEMORY
中文描述： MuxOneNAND閃存
文件頁數(shù)： 103/124頁
文件大小： 1550K
代理商： KFN2G16Q2M-DED6
MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
FLASH MEMORY
103
NOTE:
1. If OE is disabled at the same time or before CE is disabled, the output will go to high-z by t
OEZ
.
If CE is disabled at the same time or before OE is disabled, the output will go to high-z by t
CEZ
.
If CE and OE are disabled at the same time, the output will go to high-z by t
OEZ
.
These parameters are not 100% tested.
2. This Parameter is valid at toggle bit timing in asynchronous read only. (timing diagram 6.14 and 6.15)
Parameter
Symbol
KFM1G16Q2M
Unit
Min
Max
Access Time from CE Low
t
CE
-
76
ns
Asynchronous Access Time from AVD Low
t
AA
-
76
ns
Asynchronous Access Time from address valid
t
ACC
-
76
ns
Read Cycle Time
t
RC
76
-
ns
AVD Low Time
t
AVDP
12
-
ns
Address Setup to rising edge of AVD
t
AAVDS
5
-
ns
Address Hold from rising edge of AVD
t
AAVDH
7
-
ns
Output Enable to Output Valid
t
OE
-
20
ns
CE Setup to AVD falling edge
t
CA
0
-
ns
CE Disable to Output & RDY High Z
1)
t
CEZ
-
20
ns
OE Disable to Output High Z
1)
t
OEZ
-
17
ns
AVD High to OE Low
t
AVDO
0
-
ns
CE Low to RDY Valid
t
CER
-
15
ns
WE Disable to AVD Enable
t
WEA
15
-
ns
Address to OE low
t
ASO
2)
10
-
ns
5.6 AC Characteristics for Warm Reset (RP), Hot Reset
and NAND Flash Core Reset
See Timing Diagrams 6.10, 6.11 and 6.12
5.5 AC Characteristics for Asynchronous Read
See Timing Diagrams 6.3, 6.4, 6.14 and 6.15
Note:
1. These parameters are tested based on INT bit of interrupt register. Because the time on INT pin is related to the pull-up and pull-down resistor value.
2. The device may reset if tRP < tRP min(200ns), but this is not guaranteed.
Parameter
Symbol
Min
Max
Unit
RP & Reset Command Latch to BootRAM Access
tReady1
(BufferRAM)
-
5
μ
s
RP & Reset Command Latch(During Load Routines) to INT High (Note1)
tReady2
(NAND Flash Array)
-
10
μ
s
RP & Reset Command Latch(During Program Routines) to INT High (Note1)
tReady2
(NAND Flash Array)
-
20
μ
s
RP & Reset Command Latch(During Erase Routines) to INT High (Note1)
tReady2
(NAND Flash Array)
-
500
μ
s
RP & Reset Command Latch(NOT During Internal Routines) to INT High (Note1)
tReady2
(NAND Flash Array)
-
10
μ
s
RP Pulse Width (Note2)
tRP
200
-
ns
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