參數(shù)資料
型號: KAD5514P-12Q72
廠商: Intersil
文件頁數(shù): 21/34頁
文件大小: 0K
描述: IC ADC 14BIT 125MSPS SGL 72-QFN
產(chǎn)品培訓模塊: High-Speed Analog-to-Digital Converters
標準包裝: 1
系列: FemtoCharge™
位數(shù): 14
采樣率(每秒): 125M
數(shù)據(jù)接口: 串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 376mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤
供應商設備封裝: 72-QFN(10x10)
包裝: 托盤
輸入數(shù)目和類型: 1 個差分,單極
28
FN6804.2
September 10, 2009
60-6F
reserved
Reserved
G
loba
lDevice
C
onf
ig/C
ont
rol
70
reserved
Reserved
71
phase_slip
Reserved
Next
Clock
Edge
00h
G
72
clock_divide
Clock Divide [2:0]
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
other codes = reserved
00h
NOT
affected by
Soft Reset
G
73
output_mode_A
Output Mode [2:0]
000 = Pin Control
001 = LVDS 2mA
010 = LVDS 3mA
100 = LVCMOS
other codes = reserved
Output Format [2:0]
000 = Pin Control
001 = Twos Complement
010 = Gray Code
100 = Offset Binary
other codes = reserved
00h
NOT
affected by
Soft Reset
G
74
output_mode_B
DLL Range
0 = fast
1 = slow
DDR
Enable
(Note 13)
00h
NOT
affected by
Soft Reset
G
75
config_status
XOR
Result
XOR
Result
Read Only
G
76-BF
reserved
Reserved
Device
T
est
C0
test_io
User Test Mode [1:0]
00 = Single
01 = Alternate
10 = Reserved
11 = Reserved
Output Test Mode [3:0]
00h
G
0 = Off
1 = Midscale Short
2 = +FS Short
3 = -FS Short
4 = Checker Board
5 = reserved
6 = reserved
7 = One/Zero Word
Toggle
8 = User Input
9-15 = reserved
C1
Reserved
00h
G
C2
user_patt1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
G
C3
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
G
C4
user_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
G
C5
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
G
C6-FF
reserved
Reserved
NOTE:
13. At power-up, the DDR Enable bit is at a logic ‘0’ for the 72 pin package and set to a logic ‘1’ internally for the 48 pin package by an internal pull-up..
TABLE 16. SPI MEMORY MAP (Continued)
Addr
(Hex)
Parameter
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Def. Value
(Hex)
Indexed/
Global
KAD5514P
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