參數(shù)資料
型號(hào)： KAD5514P-12Q72
廠商： Intersil
文件頁數(shù)： 11/34頁
文件大小： 0K
描述： IC ADC 14BIT 125MSPS SGL 72-QFN
產(chǎn)品培訓(xùn)模塊： High-Speed Analog-to-Digital Converters
標(biāo)準(zhǔn)包裝： 1
系列： FemtoCharge™
位數(shù)： 14
采樣率（每秒）： 125M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 376mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤
輸入數(shù)目和類型： 1 個(gè)差分，單極
19
FN6804.2
September 10, 2009
Analog Input
A single fully differential input (VINP/VINN) connects to the
sample and hold amplifier (SHA) of each unit ADC. The ideal
full-scale input voltage is 1.45V, centered at the VCM voltage
of 0.535V as shown in Figure 27.
Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias the inputs as shown in
Figures 28 through 30. An RF transformer will give the best
noise and distortion performance for wideband and/or high
intermediate frequency (IF) inputs. Two different transformer
input schemes are shown in Figures 28 and 29.
This dual transformer scheme is used to improve
common-mode rejection, which keeps the common-mode
level of the input matched to VCM. The value of the shunt
resistor should be determined based on the desired load
impedance. The differential input resistance of the
KAD5514P is 500
Ω.
The SHA design uses a switched capacitor input stage
(see Figure 43), which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
This causes a disturbance at the input which must settle
before the next sampling point. Lower source impedance will
result in faster settling and improved performance. Therefore
a 1:1 transformer and low shunt resistance are
recommended for optimal performance.
A differential amplifier, as shown in Figure 30, can be used in
applications that require dc-coupling. In this configuration
the amplifier will typically dominate the achievable SNR and
distortion performance.
Clock Input
The clock input circuit is a differential pair (see Figure 44 on
page 29). Driving these inputs with a high level (up to
1.8VP-P on each input) sine or square wave will provide the
lowest jitter performance. A transformer with 4:1 impedance
ratio will provide increased drive levels.
The recommended drive circuit is shown in Figure 31. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may
impact SNR performance. The clock inputs are internally
self-biased to AVDD/2 to facilitate AC coupling.
A selectable 2x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with
a sample clock equal to twice the desired sample rate. This
allows the use of the Phase Slip feature, which enables
synchronization of multiple ADCs.
FIGURE 27. ANALOG INPUT RANGE
1.0
1.8
0.6
0.2
1.4
INP
INN
VCM
0.535V
0.725V
FIGURE 28. TRANSFORMER INPUT FOR GENERAL
PURPOSE APPLICATIONS
ADT1-1WT
0.1F
KAD5514P
VCM
ADT1-1WT
1000pF
FIGURE 29. TRANSMISSION-LINE TRANSFORMER INPUT
FOR HIGH IF APPLICATIONS
ADTL1-12
0.1F
KAD5514P
VCM
ADTL1-12
1000pF
FIGURE 30. DIFFERENTIAL AMPLIFIER INPUT
KAD5514P
VCM
0.1F
0.22F
69.8O
49.9O
100O
69.8O
348O
CM
217O
25O
Ω
FIGURE 31. RECOMMENDED CLOCK DRIVE
TC4-1W
200pF
200O
200pF
CLKP
CLKN
1000pF
Ω
KAD5514P
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KAD5514P-21Q72 制造商:Intersil Corporation 功能描述:14-BIT, 210MSPS SINGLE-CHANNEL ADC, PROGRAMMABLE LVDS/LVCMOS - Rail/Tube 制造商:Intersil Corporation 功能描述:IC ADC 14BIT 210MSPS SGL 72-QFN
KAD5514P-25Q48 制造商:Intersil Corporation 功能描述:14-BIT, 250MSPS SINGLE-CHANNEL ADC, PROGRAMMABLE LVDS/LVCMOS - Rail/Tube 制造商:Intersil Corporation 功能描述:IC ADC 14BIT 250MSPS SGL 48-QFN 制造商:Intersil Corporation 功能描述:IC, ADC, 14BIT, Resolution (Bits):14bit, Sampling Rate:250MSPS, Supply Voltage T 制造商:Intersil Corporation 功能描述:IC, ADC, 14BIT, Resolution (Bits):14bit, Sampling Rate:250MSPS, Supply Voltage Type:Single, Supply Voltage Min:1.7V, Supply Voltage Max:1.9V, Supply Current:170mA, Digital IC Case Style:QFN, No. of Pins:48, Data Interface:SPI, MSL:- , RoHS Compliant: Yes
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