參數(shù)資料
型號： K9S6408V0C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： SmartMedia CARD
中文描述： SmartMedia卡
文件頁數(shù)： 26/31頁
文件大?。?/td> 481K
代理商： K9S6408V0C
K9S2808V0C/B
26
SmartMedia
TM
K9S5608V0C/B
K9S6408V0C/B
Figure 10. Sequential Row Read2 Operation
PAGE PROGRAM
The device is programmed basically on a page basis, however it does allow multiple partial page programing of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation has the limit by its density. (See the Table of Program/Erase Characteristics) It is advis-
able not to program more often than recommend. It might cause failures due to disturbance when it exceeds its limits. The failure
mode could be that data "1" of the erased cell might be changed into data"0"of the programmed cell.
The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which
up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is
programmed into the appropriate cell. Serial data loading can be started from the 2nd half array by moving pointer. About the pointer
operation, please refer to the attached technical notes.The serial data loading period begins by inputting the Serial Data Input com-
mand(80h), followed by the three cycle address input and then serial data loading. The bytes other than those to be programmed do
not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previ-
ously entering the serial data will not initiate the programming process. The internal write-controller automatically executes the algo-
rithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process
starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The system controller
can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the
Read Status command and Reset command are valid while programming is in progress. When the Page Program is completed, the
Write Status Bit(I/O 0) may be checked(Figure 11). The internal write verify detects only errors for "1"s that are not successfully pro-
grammed to "0"s. The command register remains in Read Status command mode until another valid command is written to the com-
mand register.
50h
A
0
~ A
3
& A
9
~ A
24
I/O
0
~
7
R/B
Start Add.(3Cycle)
Data Output
Data Output
Data Output
2nd
Nth
(16Byte)
(16Byte)
1st
Figure 11. Program & Read Status Operation
80h
A
0
~ A
7
& A
9
~ A
24
528 Byte Data
I/O
0
~
7
R/B
Address & Data Input
I/O
0
Pass
10h
70h
Fail
t
R
t
R
t
R
t
PROG
≈
(A
4
~ A
7
:
Don
t Care)
Data Field
Spare Field
1st
Block
Nth
A
22
: K9S6408V0X
A
23
: K9S2808V0X
A
24
: K9S5608V0X
A
22
: K9S6408V0X
A
23
: K9S2808V0X
A
24
: K9S5608V0X
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