參數(shù)資料
型號： K9S6408V0C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： SmartMedia CARD
中文描述： SmartMedia卡
文件頁數(shù)： 10/31頁
文件大?。?/td> 481K
代理商： K9S6408V0C
K9S2808V0C/B
10
SmartMedia
TM
K9S5608V0C/B
K9S6408V0C/B
MODE SELECTION
NOTE
: 1. X can be V
IL
or V
IH.
2. WP should be biased to CMOS high or CMOS low for standby.
CLE
H
L
H
L
L
L
X
X
X
X
X
ALE
L
H
L
H
L
L
X
X
X
X
(1)
X
CE
L
L
L
L
L
L
L
X
X
X
H
WE
RE
H
H
H
H
H
WP
X
X
H
H
H
X
X
H
H
L
Mode
Read Mode
Command Input
Address Input(3clock)
Command Input
Address Input(3clock)
Write Mode
Data Input
sequential Read & Data Output
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
Stand-by
H
X
X
X
X
X
X
X
X
X
X
0V/V
CC
(2)
CAPACITANCE
(
T
A
=25
°
C, V
CC
=3.3V, f=1.0MHz)
NOTE
: Capacitance is periodically sampled and not 100% tested.
Item
Symbol
C
I/O
C
IN
Test Condition
V
IL
=0V
V
IN
=0V
Min
-
-
Max
10
10
Unit
pF
pF
Input/Output Capacitance
Input Capacitance
VALID BLOCK
NOTE
:
1. The
K9SXX08V0X
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
. Do not
erase or program factory-marked bad blocks.
Refer to the attached technical notes for an appropriate management of invalid blocks.
2. Per the specification of the physical format version 1.2 by SSFDC forum, minimum 1,000 vaild blocks are guaranteed for each 16MB memory space.
(Refer to the attached technical notes)
Parameter
Symbol
Min
1,014
1,004
2013
Typ.
1,020
-
-
Max
1,024
1,024
2048
Unit
Valid Block Number
K9S6408V0X
K9S2808V0X
K9S5608V0X
N
VB
Blocks
Program/Erase Characteristics
Parameter
Symbol
t
PROG
Min
-
Typ
200
Max
500
2
3
3
Unit
μ
s
cycles
cycles
ms
Program Time
Number of Partial Program Cycles
in the Same Page
Main Array
Spare Array
Nop
-
-
Block Erase Time
t
BERS
-
2
AC TEST CONDITION
(T
A
=0 to 55
°
C, V
CC
=2.7V~3.6V unless otherwise noted)
Parameter
Value
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load (3.0V +/-10%)
Output Load (3.3V +/-10%)
0.4V to 2.4V
5ns
1.5V
1 TTL GATE and CL=50pF
1 TTL GATE and CL=100pF
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