參數(shù)資料
型號： K5A3280YTC-T755
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： MCP MEMORY
中文描述： MCP的記憶
文件頁數(shù)： 41/45頁
文件大?。?/td> 625K
代理商： K5A3280YTC-T755
MCP MEMORY
K5A3x80YT(B)C
Revision 0.0
November 2002
- 41 -
Preliminary
SRAM DATA RETENTION CHARACTERISTICS
1. CS1
S
≥
Vcc
S
-0.2V, CS2
S
≥
Vcc
S
-0.2V(CS1
S
controlled) or CS2
S
≤
0.2V(CS2
S
controlled)
2. Typical values are measured at Vcc=3.0V, Ta=25
°
C , not 100% tested.
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc
S
for data retention
Data retention current
V
DR
CS1
S
≥
Vcc
S
-0.2V
Vcc
S
=3.0V, CS1
S
≥
Vcc
S
-0.2V
1.5
-
3.3
V
I
DR
-
0.5
15
μ
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ns
Recovery time
t
RDR
tRC
-
-
SRAM AC CHARACTERISTICS
Parameter List
Symbol
55ns
Units
Min
Max
Read
Read cycle time
t
RC
55
-
ns
Address access time
t
AA
-
55
ns
Chip select to output
t
CO1
, t
CO2
-
55
ns
Output enable to valid output
t
OE
-
25
ns
UB, LB Access Time
t
BA
-
55
ns
Chip select to low-Z output
t
LZ1
, t
LZ2
10
-
ns
UB, LB enable to low-Z output
t
BLZ
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
ns
Chip disable to high-Z output
t
HZ1
, t
HZ2
0
20
ns
UB, LB disable to high-Z output
t
BHZ
0
20
ns
Output disable to high-Z output
t
OHZ
0
20
ns
Output hold from address change
t
OH
10
-
ns
Write
Write cycle time
t
WC
55
-
ns
Chip select to end of write
t
CW
45
-
ns
Address set-up time
t
AS
0
-
ns
Address valid to end of write
t
AW
45
-
ns
UB, LB Valid to End of Write
t
BW
45
-
ns
Write pulse width
t
WP
40
-
ns
Write recovery time
t
WR
0
-
ns
Write to output high-Z
t
WHZ
0
20
ns
Data to write time overlap
t
DW
20
-
ns
Data hold from write time
t
DH
0
-
ns
End write to output low-Z
t
OW
5
-
ns
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