參數(shù)資料
型號(hào)： K4T1G044QA-ZCE6
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 1Gb A-die DDR2 SDRAM Specification
中文描述： 1GB的芯片DDR2內(nèi)存規(guī)格
文件頁(yè)數(shù)： 14/28頁(yè)
文件大?。?/td> 612K
代理商： K4T1G044QA-ZCE6
Page 14 of 28
Rev. 1.1 Aug. 2005
DDR2 SDRAM
1G A-die DDR2 SDRAM
OCD default characteristics
Notes:
1. Absolute Specifications (0°C
≤
T
CASE
≤
+95°C; V
DD
= +1.8V ±0.1V, V
DDQ
= +1.8V ±0.1V)
2. Impedance measurement condition for output source dc current: V
DDQ
= 1.7V; V
OUT
= 1420mV; (V
OUT
-V
DDQ
)/Ioh must be less than 23.4 ohms for val-
ues of V
OUT
between V
DDQ
and V
DDQ
-280mV. Impedance measurement condition for output sink dc current: V
DDQ
= 1.7V; V
OUT
= 280mV; V
OUT
/
Iol must be less than 23.4 ohms for values of V
OUT
between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from V
IL
(AC) to V
IH
(AC).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaran-
teed by design and characterization.
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty.
Output slew rate load :
7. DRAM output slew rate specification applies to 400Mb/sec/pin, 533Mb/sec/pin and 667Mb/sec/pin speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification.
Description
Parameter
Min
Nom
Max
Unit
Notes
Output impedance
12.6
18
23.4
ohms
1,2
Output impedance step size for OCD calibration
0
1.5
ohms
6
Pull-up and pull-down mismatch
0
4
ohms
1,2,3
Output slew rate
Sout
1.5
5
V/ns
1,4,5,6,7,8
25 ohms
VTT
Output
(VOUT)
Reference
Point
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