參數(shù)資料
型號(hào)： K4N56163QF-GC30
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256Mbit gDDR2 SDRAM
中文描述： 片256Mbit GDDR2 SDRAM的
文件頁(yè)數(shù)： 6/73頁(yè)
文件大?。?/td> 1262K
代理商： K4N56163QF-GC30
- 6 -
Rev 1.6 (Apr. 2005)
256M gDDR2 SDRAM
K4N56163QF-GC
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
CK, CK
Input
Clock:
CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the pos-
itive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK
(both directions of crossing).
Clock Enable:
CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input
buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation
(all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down
entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be main-
tained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled
during power-down. Input buffers, excluding CKE, are disabled during self refresh.
Chip Select:
All commands are masked when CS is registered HIGH. CS provides for external bank
selection on systems with multiple banks. CS is considered part of the command code.
On Die Termination:
ODT (registered HIGH) enables termination resistance internal to the gDDR2
SDRAM. When enabled, ODT is only applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM
signal for x16 configurations. The ODT pin will be ignored if the Extended Mode Register (EMRS) is pro-
grammed to disable ODT.
Command Inputs:
RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM is sampled
HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
Bank Address Inputs:
BA0 and BA1 define to which bank an Actove, Read, Write or Precharge com-
mand is being applied. BA0 also determines if the mode register or extended mode register is to be
accessed during a MRS or EMRS cycle.
Address Inputs:
Provided the row address for Active commands and the column address and Auto Pre-
charge bit for Read/Write commands to select one location out of the memory array in the respective
bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one
bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by
BA0, BA1. The address inputs also provide the op-code during Mode Register Set commands.
CKE
Input
CS
Input
ODT
Input
RAS, CAS, WE
Input
(L)UDM
Input
BA0 - BA1
Input
A0 - A12
Input
DQ
Input/
Output
Data Input/ Output:
Bi-directional data bus.
LDQS,(LDQS)
UDQS,(UDQS)
Input/
Output
Data Strobe:
output with read data, input with write data. Edge-aligned with read data, centered in write
data. LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. The
data strobes LDQS and UDQS may be used in single ended mode or paired with optional complementary
signals LDQS and UDQS to provide differential pair signaling to the system during both reads and writes.
An EMRS(1) control bit enables or disables all complementary data strobe signals.
NC/RFU
V
DDQ
V
SSQ
V
DDL
V
SSL
V
DD
V
SS
V
REF
No Connect:
No internal electrical connection is present.
Supply
DQ Power Supply:
1.8V ± 0.1V
Supply
DQ Ground
Supply
DLL Power Supply:
1.8V ± 0.1V
Supply
DLL Ground
Supply
Power Supply:
1.8V ± 0.1V
Supply
Ground
Supply
Reference voltage
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