參數(shù)資料
型號: K4H510438B-TCA0
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Enclosure; For Use With:PC17/16-L3, -3, -LFC3, FC3 Cardmaster Polycarbonate Enclosure; Approval Bodies:UL, CSA; External Height:5.4"; External Width:5.2"; Features:Impact Resistant EN 50102; UV Resistant to UL 508
中文描述: 128MB DDR SDRAM的
文件頁數(shù): 12/24頁
文件大?。?/td> 367K
代理商: K4H510438B-TCA0
Rev. 1.1 June. 2005
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
IDD7A : Operating current: Four bank operation
1. Typical Case: Fro DDR200,266,333: Vdd = 2.5V, T=25’C; For DDR400: Vdd=2.6V,T=25’C
Worst Case : Vdd = 2.7V, T= 10’ C
2. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*50% of data changing at every burst
- A2(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*50% of data changing at every burst
- B3(166Mhz,CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*50% of data changing at every burst
- CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT
IDD1 : Operating current: One bank operation
1. Typical Case: Fro DDR200,266,333: Vdd = 2.5V, T=25’C; For DDR400: Vdd=2.6V,T=25’C
Worst Case : Vdd = 2.7V, T= 10’c
2. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
3. Timing patterns
- B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK
Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- A2 (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK
Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- B3(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=3*tCK, tRC = 10*tCK, tRAS=7*tCK
Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT
14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A
相關PDF資料
PDF描述
K4H510438B-TCA2 Enclosure; For Use With:PC21/28-1 USA Cardmaster Polycarbonate Enclosure; Approval Bodies:UL, CSA; External Height:7.9"; External Width:5.6"; Features:Impact Resistant EN 50102; UV Resistant to UL 508
K4H510438B-TCB0 Enclosures; For Use With:PC30/25-1 USA Cardmaster Polycarbonate Enclosure; Approval Bodies:UL, CSA; External Height:11.4"; External Width:7.5"; Features:Impact Resistant EN 50102; UV Resistant to UL 508 RoHS Compliant: Yes
K4H510438B-TLA0 Enclosures; For Use With:PC36/31-1 USA Cardmaster Polycarbonate Enclosure; Approval Bodies:UL, CSA; Features:Impact Resistant EN 50102; UV Resistant to UL 508; Approval Categories:Flammability Rated UL94-5V; Protection Rated IP65
K4H510438B-TLA2 128Mb DDR SDRAM
K4H510438B-TLB0 MOUNTING PLATE, STEEL, FOR TA201610; Length / Height, external:170mm; Material:Steel; Thickness, material:1.5mm; Width, external:140mm RoHS Compliant: Yes
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