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參數(shù)資料
| 型號： | K1S3216BCD |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2Mx16 bit Page Mode Uni-Transistor Random Access Memory |
| 中文描述： | 2Mx16位頁面模式統(tǒng)一晶體管隨機存取存儲器 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 168K |
| 代理商： | K1S3216BCD |
Revision 1.0
April 2005
K1S3216BCD
- 6 -
U
t
RAM
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to Vcc-0.2V
Input rising and falling time: 5ns
Input and output reference voltage: 0.5 x V
CC
Output load (See right): C
L
=50pF
C
L
1. Including scope and jig capacitance
Dout
AC CHARACTERISTICS
(Vcc=1.7~2.0V, T
A
=-40 to 85
°
C)
1. t
WP
(min)=70ns or t
WC
(min)=90ns for continuous write operation over 50 times.
Parameter List
Symbol
Speed Bins
Units
70ns
85ns
Min
Max
Min
Max
Common
CS High Pulse Width
t
CSHP
10
-
10
-
ns
Read
Read Cycle Time
t
RC
70
-
85
-
ns
Address Access Time
t
AA
-
70
-
85
ns
Chip Select to Output
t
CO
-
70
-
85
ns
Output Enable to Valid Output
t
OE
-
35
-
40
ns
UB, LB Access Time
t
BA
-
70
-
85
ns
Chip Select to Low-Z Output
t
LZ
10
-
10
-
ns
UB, LB Enable to Low-Z Output
t
BLZ
10
-
10
-
ns
Output Enable to Low-Z Output
t
OLZ
5
-
5
-
ns
Chip Disable to High-Z Output
t
HZ
0
25
0
25
ns
UB, LB Disable to High-Z Output
t
BHZ
0
25
0
25
ns
Output Disable to High-Z Output
t
OHZ
0
25
0
25
ns
Output Hold from Address Change
t
OH
3
-
3
-
ns
Page Cycle
t
PC
25
-
25
-
ns
Page Access Time
t
PA
-
20
-
20
ns
Write
Write Cycle Time
t
WC
70
-
85
-
ns
Chip Select to End of Write
t
CW
60
-
70
-
ns
Address Set-up Time
t
AS
0
-
0
-
ns
Address Valid to End of Write
t
AW
60
-
70
-
ns
UB, LB Valid to End of Write
t
BW
60
-
70
-
ns
Write Pulse Width
t
WP
55
1)
-
60
1)
-
ns
Write Recovery Time
t
WR
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
25
0
25
ns
Data to Write Time Overlap
t
DW
30
-
35
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
ns
End Write to Output Low-Z
t
OW
5
-
5
-
ns
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