- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384576 > JS28F640P30B85 (INTEL CORP) Intel StrataFlash Embedded Memory PDF資料下載
參數(shù)資料
| 型號(hào)： | JS28F640P30B85 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | Intel StrataFlash Embedded Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 85 ns, PDSO56 |
| 封裝： | 14 X 20 MM, LEAD FREE, TSOP-56 |
| 文件頁(yè)數(shù)： | 57/102頁(yè) |
| 文件大?。?/td> | 1609K |
| 代理商： | JS28F640P30B85 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)當(dāng)前第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
57
10.3.3
WAIT Polarity
The WAIT Polarity bit (WP), RCR[10] determines the asserted level (V
OH
or V
OL
) of WAIT.
When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is asserted low.
WAIT changes state on valid clock edges during active bus cycles (CE# asserted, OE# asserted,
RST# deasserted).
10.3.3.1
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-array read mode, such as read status, read ID, or
read query. The WAIT signal is also “deasserted” when data is valid on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works correctly only
on the first data access.
When the device is operating in asynchronous page mode, asynchronous single word read mode,
and all write operations, WAIT is set to a deasserted state as determined by RCR[10]. See
Figure
17, “Asynchronous Single-Word Read (ADV# Latch)” on page 38
, and
Figure 18, “Asynchronous
Page-Mode Read Timing” on page 39
.
Figure 29.
Example Latency Count Setting using Code 3
CLK
CE#
ADV#
A[MAX:0]
D[15:0]
t
Data
Code 3
Address
Data
0
1
2
3
4
R103
High-Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| JS28F128P30T85 | Intel StrataFlash Embedded Memory |
| JS28F256P30B85 | Intel StrataFlash Embedded Memory |
| JS28F256P30T85 | Intel StrataFlash Embedded Memory |
| JS28F640P30T85 | Intel StrataFlash Embedded Memory |
| JS28F128P30B85 | Intel StrataFlash Embedded Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| JS28F640P30B85A | 功能描述:IC FLASH 64MBIT 85NS 56TSOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:StrataFlash™ 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
| JS28F640P30BF65D | 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Trays |
| JS28F640P30BF75A | 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel/Serial 1.8V 64Mbit 4M x 16bit 75ns 56-Pin TSOP Tray 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 4MX16 PBF TSOP 1.8V 制造商:Micron Technology 功能描述:NOR Flash Parallel/Serial 1.8V 64Mbit 4M x 16bit 75ns 56-Pin TSOP Tray |
| JS28F640P30BF75D | 制造商:Micron Technology Inc 功能描述:PARALLEL NOR - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 75NS 56TSOP |
| JS28F640P30T85 | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:Numonyx StrataFlash Embedded Memory |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。