參數(shù)資料
型號: ITF86110DK8T
廠商: INTERSIL CORP
元件分類: 功率晶體管
英文描述: 7.5A, 30V, 0.025 Ohm, Dual N-Channel, Logic Level, Power MOSFET
中文描述: 30 V, 0.034 ohm, 2 CHANNEL, N-CHANNEL, Si, POWER, MOSFET, MS-012AA
封裝: PLASTIC, SO-8
文件頁數(shù): 7/13頁
文件大小: 200K
代理商: ITF86110DK8T
7
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
JM
, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
DM
, in an
application. Therefore the application’s ambient temperature,
T
A
(
o
C), and thermal resistance R
θ
JA
(
o
C/W) must be
reviewed to ensure that T
JM
is never exceeded. Equation 1
mathematically represents the relationship and serves as
the basis for establishing the rating of the part.
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
DM
is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 20 defines the
R
θ
JA
for the device as a function of the top copper
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve.
Displayed on the curve are R
θ
JA
values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
P
DM
.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 20 or by calculation using
Equation 2. R
θ
JA
is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
ln
×
=
While Equation 2 describes the thermal resistance of a
single die, several devices are offered with two die in the
SO8 package. The dual die SO8 package introduces an
additional thermal component, thermal coupling resistance,
R
θβ
. Equation 3 describes
R
θβ
as a function of the top
copper mounting pad area.
R
θβ
46.4
21.7
Area
ln
=
The thermal coupling resistance vs. copper area is also
graphically depicted in Figure 20. It is important to note the
thermal resistance (R
θ
JA
) and thermal coupling resistance
(
R
θβ
) are equivalent for both die. For example at 0.1 square
inches of copper:
R
θ
JA1
= R
θ
JA2
= 159C/W
R
θβ
1
=
R
θβ
2
= 97C/W
T
J1
and T
J2
define the junction temperature of the
respective die. Similarly, P
1
and P
2
define the power
dissipated in each die. The steady state junction
temperature can be calculated using Equation 4 for die 1
and Equation 5 for die 2.
Example: To calculate the junction temperature of each die
when die 2 is dissipating 0.5 Watts and die 1 is dissipating 0
Watts. The ambient temperature is 70C and the package is
mounted to a top copper area of 0.1 square inches per die.
Use Equation 4 to calculate T
J1
and Equation 5 to calculate
T
J2
.
.
T
J1
= (0 Watts)(159C/W) + (0.5 Watts)(97C/W) + 70C
T
J1
= 119C
T
J2
= (0.5 Watts)(159C/W) + (0 Watts)(97C/W) + 70C
T
J2
= 150C
(EQ. 1)
PDM
θ
JA
(
------------------------------
)
=
(EQ. 2)
R
θ
JA
103.2
24.3
Area
(
)
0
0.001
50
100
150
200
250
300
0.01
0.1
1
R
θ
,
θ
J
(
o
C
AREA, TOP COPPER AREA (in
2
) PER DIE
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA
191
o
C/W - 0.027in
2
228
o
C/W - 0.006in
2
R
θ
JA
= 103.2 - 24.3
*
ln
(AREA)
R
θβ
= 46.4 - 21.7
*
ln
(AREA)
(EQ. 3)
(
)
×
(EQ. 4)
TJ1
P1R
θ
JA
P2
R
θβ
TA
+
+
=
(EQ. 5)
TJ2
P2R
θ
JA
P1
R
θβ
TA
+
+
=
ITF86110DK8T
相關PDF資料
PDF描述
ITF86116SQT 10A, 30V, 0.012 Ohm, N-Channel, Logic Level, Power MOSFET
ITF86172SK8T 10A, 30V, 0.016 Ohm, P-Channel, Logic Level, Power MOSFET
ITF86174SQT 8360 TBGA C ENCRP
ITF87008DQT Dual N-Channel,Specified Power MOSFET(雙N溝道邏輯電平功率MOS場效應管)
ITF87052SVT 3A, 20V, 0.115 Ohm, P-Channel,2.5V Specified Power MOSFET(3A, 20V, 0.115Ω P溝道2.5V專用功率MOS場效應管)
相關代理商/技術參數(shù)
參數(shù)描述
ITF86116SQT 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:10A, 30V, 0.012 Ohm, N-Channel, Logic Level, Power MOSFET
ITF86116SQT2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | 9A I(D) | TSSOP
ITF86130SK8T 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:14A, 30V, 0.0078 Ohm, N-Channel, Logic Level, Power MOSFET
ITF86172SK8T 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:10A, 30V, 0.016 Ohm, P-Channel, Logic Level, Power MOSFET
ITF86174SQT 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:9A, 30V, 0.016 Ohm, P-Channel, Logic Level, Power MOSFET