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| 型號： | IT80C52EXXX-30SHXXX:R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 60/60頁 |
| 文件大?。?/td> | 5137K |
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9
8266D-MCU Wireless-06/12
ATmega128RFA1
7 AVR CPU Core
7.1 Introduction
This section discusses the AVR core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to
access memories, perform calculation, control peripherals, and handle interrupts.
7.2 Architectural Overview
Figure 7-1.Block Diagram of the AVR Architecture
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
D
ire
ct
Ad
d
re
ssi
n
g
In
d
ire
ct
Ad
d
re
ssi
n
g
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n
In order to maximize performance and parallelism, the AVR uses a Harvard
architecture – with separate memories and buses for program and data. Instructions in
the program memory are executed with a single level pipelining. While one instruction is
being executed, the next instruction is pre-fetched from the program memory. This
concept enables instructions to be executed in every clock cycle. The program memory
is In-System Reprogrammable Flash memory.
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