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參數(shù)資料
| 型號： | IT80C52EXXX-30SHXXX:R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 18/60頁 |
| 文件大小： | 5137K |
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25
8266D-MCU Wireless-06/12
ATmega128RFA1
8.4.3 EEDR – EEPROM Data Register
Bit
7
6
5
4
3
2
1
0
$20 ($40)
EEDR7:0
EEDR
Read/Write
RW
Initial Value
0
For the EEPROM write operation, the EEDR Register contains the data to be written to
the EEPROM in the address given by the EEAR Register. For the EEPROM read
operation, the EEDR contains the data read out from the EEPROM at the address given
by EEAR.
Bit 7:0 – EEDR7:0 - EEPROM Data
8.4.4 EECR – EEPROM Control Register
Bit
7
6
5
4
3
2
1
0
$1F ($3F)
Res1
Res0
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
EECR
Read/Write
R
RW
Initial Value
0
X
0
X
0
Bit 7:6 – Res1:0 - Reserved
Bit 5:4 – EEPM1:0 - EEPROM Programming Mode
The EEPROM Programming mode bit setting defines which programming action will be
triggered when writing EEPE. It is possible to program data in one atomic operation
(erase the old value and program the new value) or to split the Erase and Write
operations in two different operations. While EEPE is set, any write to EEPM1:0 will be
ignored. During reset, the EEPM1:0 bits will be reset to 0 unless the EEPROM is busy
programming.
Table 8-4 EEPM Register Bits
Register Bits
Value
Description
0x00
Erase and Write in one operation (Atomic
Operation)
0x01
Erase only
0x02
Write only
EEPM1:0
0x03
Reserved for future use
Bit 3 – EERIE - EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.
Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a
constant interrupt when EEPE is cleared.
Bit 2 – EEMPE - EEPROM Master Write Enable
The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be
written. When EEMPE is set, setting EEPE within four clock cycles will write data to the
EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect.
When EEMPE has been written to one by software, hardware clears the bit to zero after
four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.
Bit 1 – EEPE - EEPROM Programming Enable
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