參數(shù)資料
型號: ISPPAC81
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable Analog Circuit
中文描述: 在系統(tǒng)可編程模擬電路
文件頁數(shù): 4/20頁
文件大?。?/td> 176K
代理商: ISPPAC81
Lattice Semiconductor
ispPAC81 Data Sheet
4
Pin Descriptions
Connection Notes
1.
All inputs and outputs are labeled with plus (+) and minus (-) signs. Polarity is labeled for reference and can be
selected externally by reversing pin connections.
2.
All analog output pins are “hard-wired” to internal output devices and should be left open if not used. V
V
OUT-
should not be tied together as unnecessary power will be dissipated.
3.
When the signal input is single-ended, the other half of the unused differential input must be connected to a DC
common-mode reference (usually VREF
OUT
, 2.5V).
OUT+
and
Absolute Maximum Ratings
Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V
Logic and Analog Input Voltage Applied. . . . . . . . . . . . . . .0 to VS
Logic and Analog Output Short Circuit Duration . . . . . . Inde
fi
nite
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . . . .260°C
Ambient Temperature with Power Applied . . . . . . . . -55 to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
Note: Stresses above those listed may cause permanent damage to the device. These are stress only ratings and functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this speci
fi
cation
is not implied.
Pin(s)
1
Symbol
TMS
Name
Description
Test Mode Select
Serial interface logic mode select pin (input). JTAG interface
mode only.
Serial interface logic clock pin (input). JTAG and SPI interface
modes.
Serial interface logic pin (input) for both JTAG and SPI opera-
tion modes.
Serial interface logic pin (output) for both JTAG and SPI opera-
tion modes. Input data valid on falling edge of TCK (JTAG), or
on rising edge of CS (SPI).
Chip select logic input pin. SPI data latch.
Digital pin (input). Commands an auto-calibration sequence on
a rising edge.
Enable SPI logic input pin. When high, causes serial port to run
in SPI mode.
Ground pin. Should normally be connected to the analog
ground plane.
2
TCK
Test Clock
3
TDI
Test Data In
4
TDO
Test Data Out
5
6
CS
CAL
Chip Select
Auto-Calibrate
7
ENSPI
Enable SPI Mode
8
GND
Ground
9
VREFOUT Common-Mode Reference Common-mode voltage reference output pin (+2.5V nominal).
Must be bypassed to GND with a 1
μ
F capacitor.
IN
Inputs (+ or -)
Differential input pins, using two pins (e.g., IN+ and IN-). Plus or
minus components of V
IN
, where differential V
IN
= V
IN+
- V
IN-
.
TEST
Test Pin
Test pin. Connect to GND for proper circuit operation.
OUT
Outputs (+ or -)
Differential output pins, using two pins (e.g., OUT+ and OUT-).
Complementary with respect to VREFOUT.
Differential V
OUT
= V
OUT+
- V
OUT
-.
VS
Supply Voltage
Analog supply voltage pin (5V nominal). Should be bypassed to
GND with 1
μ
F and .01
μ
F capacitors.
10, 11
12, 15
13, 14
16
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