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參數(shù)資料
| 型號(hào)： | ISPPAC81 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | 在系統(tǒng)可編程模擬電路 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 176K |
| 代理商： | ISPPAC81 |
Lattice Semiconductor
ispPAC81 Data Sheet
11
JTAG User Bits
There are a number of user-con
fi
gured E
2
bits that control various aspects of and can all be accessed in either the
pull-down menus or directly in the schematic design entry screen of the PAC-Designer software interface to the
ispPAC81. See the online help associated with the ispPAC81 in PAC-Designer for more details of how to set/pro-
gram various operation modes. The list of control E
2
bits available is listed in Table 3.
Differential I/O
Differential peak-peak voltage is determined by knowing the signal extremes on both differential input or output
pins. For example, if V(+) equals 4V and V(-) equals 1V, the differential voltage is de
fi
ned as V(+) - V(-) = Vdiff, or
4V - 1V = +3V. Since either polarity can exist on differential I/O pins, it is also possible for the opposite extreme to
exist and would mean when V(+) equals 1V and V(-) equals 4V, the differential voltage is now 1V - 4V = -3V. To cal-
culate the differential peak-peak voltage or full signal swing, the absolute difference between the two extreme
Vdiff’s is calculated. Using the previous examples would result in |(+3V) - (-3V)| = 6V. It can be immediately seen
that true differential signals result in a doubling of usable dynamic range. For more explanation of this and other dif-
ferential circuit bene
fi
ts, please refer to application note number AN6019,
Differential Signaling.
Single-ended Input
To connect the ispPAC81 differential input to a single-ended signal, one of the differential inputs needs to be con-
nected to a DC bias, preferably VREF
OUT
. The input signal must either be AC coupled or have a DC bias equal to
the DC level of the other input. Since the input voltage is de
fi
ned as V
IN+
- V
IN-
, the common mode level is ignored.
The signal information is only present on one input, the other being connected to a voltage reference.
Single-ended Output
Connecting the output to a single-ended circuit is simpler still. Simply connect one-half of the differential output, but
not the other. Either output conveys the signal information, just at half the magnitude of the differential output. The
DC level of the single-ended output will be VREF
OUT
. If the load is not AC coupled and is at a DC potential other
than VREF
OUT
, the load draws a constant current. Using one of the differential outputs halves the available output
voltage swing (3Vp-p versus 6Vp-p). If the load requires DC current, the available voltage swing is reduced. The
output is capable of 10mA, so any DC current raises the minimum allowable load impedance.
Input Common-Mode Voltage Range
For the ispPAC81, both maximum input signal range and corresponding common-mode voltage range are a func-
tion of the input gain setting. The maximum input voltage times the gain of an individual PACblock cannot exceed
the output range of that block or clipping will occur. The maximum guaranteed input range is 1V to 4V, with a typical
range of 0.7V to 4.3V for a 5V supply voltage.
The input common-mode voltage is V
CM
= (V
CM+
+ V
CM-
)/2. When the value of V
CM
is 2.5V, there are no further
input restrictions other than the previously mentioned clipping consideration. This is easily achieved when the input
signal is true differential and referenced to 2.5V.
When V
CM
is not 2.5V and the gain setting is greater than one, distortion will occur when the maximum input limit is
reached for a particular gain. The lowest V
CM
for a given gain setting is expressed by the formula, V
CM–
= 0.675V +
0.584G·V
IN
where G is the gain setting and V
IN
is the peak input voltage, expressed as |V
IN+
- V
IN–
| and the highest
V
CM
is V
CM+
= 5.0V - V
CM–
where 5V is the nominal supply voltage.
In Table 4, the maximum V
IN
for a given V
CM–
to V
CM+
range is given. If the maximum V
IN
is known,
fi
nd the equiv-
alent or greater value under the appropriate gain column and the widest range for V
CM
will be found horizontally
across in the left-most two columns. Only a V
CM
range equal to or less than this will give distortion-free perfor-
mance. Conversely, if the maximum V
CM
range is known, the largest acceptable peak value of V
IN
can be found in
the corresponding gain column. All values of V
IN
less than this will give full rated performance.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC81-01PI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC81-01SI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ispPAC-CLK5304S-01T48C | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 ISP Zero Delay Unv F an-Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5304S-01T48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5304S-01T48I | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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