參數(shù)資料
型號(hào): ISPPAC81
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable Analog Circuit
中文描述: 在系統(tǒng)可編程模擬電路
文件頁(yè)數(shù): 14/20頁(yè)
文件大?。?/td> 176K
代理商: ISPPAC81
Lattice Semiconductor
ispPAC81 Data Sheet
14
In-System Programmability
In-System Programming
The ispPAC81 is an in-system programmable device. This is accomplished by integrating all high voltage program-
ming circuitry on-chip. Programming is performed through a 5-wire, IEEE 1149.1 compliant serial port interface at
normal logic levels. Once a device is programmed, all con
fi
guration information is stored on-chip, in non-volatile
E
2
CMOS memory cells. The speci
fi
cs of the IEEE 1149.1 serial interface are described in the interface section of
this data sheet.
User Electronic Signature
A user electronic signature (UES) feature is included in the E
2
memory of the ispPAC81. It contains 21 bits that can
be con
fi
gured by the user to store unique data such as ID codes, revision numbers or inventory control data.
Electronic Security
An electronic security “fuse” (ESF) bit is provided in every ispPAC81 device to prevent unauthorized readout of the
E
2
CMOS user bit patterns. Once programmed, this cell prevents further access to the functional user bits in the
device. This cell can only be erased by reprogramming the device, so the original con
fi
guration can not be exam-
ined once programmed. Usage of this feature is optional.
Production Programming Support
Once a
fi
nal con
fi
guration is determined, an ASCII format JEDEC
fi
le is created using the PAC-Designer software.
Devices can then be ordered through the usual supply channels with the user’s speci
fi
c con
fi
guration already pre-
loaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production pro-
gramming equipment, giving customers a wide degree of freedom and
fl
exibility in production planning.
Evaluation Fixture
Included in the basic ispPAC81 Design Kit is an engineering prototype board that can be connected to the parallel
port of a PC. It demonstrates proper layout techniques for the ispPAC81 and can be used in real time to check cir-
cuit operation as part of the design process. Input and output connections as well as a “breadboard” circuit area
are provided to speed debugging of the circuit.
Figure 4. Configuring the ispPAC81 “In-System” from a PC Parallel Port
ispDownload
Cable (6')
4
Other
System
Circuitry
ispPAC81
Device
PAC-Designer
Software
相關(guān)PDF資料
PDF描述
ISPPAC81-01PI In-System Programmable Analog Circuit
ISPPAC81-01SI In-System Programmable Analog Circuit
IT100 P-CHANNEL JFET SWITCH
IT136 Monolithic Dual PNP General Purpose Amplifier
IT136-TO71 Monolithic Dual PNP General Purpose Amplifier
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPAC81-01PI 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
ISPPAC81-01SI 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
ispPAC-CLK5304S-01T48C 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 ISP Zero Delay Unv F an-Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5304S-01T48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ispPAC-CLK5304S-01T48I 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel