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參數(shù)資料
| 型號： | ISPPAC81-01PI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 176K |
| 代理商： | ISPPAC81-01PI |
Lattice Semiconductor
ispPAC81 Data Sheet
18
Figure 7. Identification Code (IDCODE) 32-Bit Binary Word for Lattice ispPAC81
ADDUSR
(Address User Register) instruction is a Lattice-de
fi
ned instruction that selects the user register to be
shifted during a Shift-DR operation. Normal operation of a device is not interrupted by this instruction. It precedes a
PRGA or PRGB (Program User A or B) instruction to shift in a new con
fi
guration from the user register into either
the A or B con
fi
guration memory, and follows a VERA or VERB (Verify User A or B) instruction to shift out the cur-
rent con
fi
guration of either A or B con
fi
guration memory into the user register. The bit code for this instruction is
shown in Table 5.
The
PRGA
and
PRGB
(Program User A or B) are Lattice instructions that enable the data shifted into the user reg-
ister to be programmed into the non-volatile E
2
CMOS memory of the ispPAC81 and thereby alter either or both of
its two user con
fi
gurations. The user register is a 96-bit shift register that contains all the user-controlled parametric
data pertaining to the con
fi
guration of the ispPAC81. NOTE: Although the user register length is 96 bits, only the “A”
con
fi
guration is that long. The device gain setting bits, UES bits, and security fuse bit are all part of the “A” con
fi
gu-
ration memory and are not stored at all in “B” memory, which only contains the unique capacitor settings of that
con
fi
guration. When initially programming or reprogramming the ispPAC81 with software other than PAC-Designer,
or an authorized third-party programmer (e.g., via microcontroller, refer to the Lattice application note covering the
required algorithms necessary for complete JTAG device programming control of the ispPAC81, speci
fi
c bit assign-
ments, word lengths, etc.). Normal operation of the device is interrupted during the actual programming time. A
programming operation does not begin until entry of the Run-Test/Idle state. The time required to insure data reten-
tion is given in the TAP signal speci
fi
cations table. The user must ensure that the recommended programming
times are observed. The bit code for these instructions is shown in Table 5.
VERA
and
VERB
(Verify User A or B) are the next Lattice instructions and cause the current A or B con
fi
gurations
of the ispPAC81 to be loaded into the user register. This operation doesn’t interrupt operation of the device. The
current con
fi
guration of either the A or B con
fi
guration memory can then be shifted out of the user register immedi-
ately after an ADDUSR instruction is executed. NOTE: The veri
fi
cation of memory con
fi
guration “A” is possible only
when the A/B bit is set to a logic 0. This must be taken into account if verify will be performed at a later time on
parts with unknown con
fi
gurations (refer to the Lattice application note covering the required algorithms necessary
for complete JTAG device programming control of the ispPAC81, speci
fi
c bit assignments, word lengths, etc.). If the
A/B bit has been set to a logic 1, it will not be possible to do a VERA command properly. The bit code for this
instruction is shown in Table 5.
ENCAL
(Enable Calibration) is a Lattice instruction that enables the start of an auto-calibration sequence. This
operation causes all outputs of the device to go to 2.5V until the calibration sequence is completed (see Timing
Speci
fi
cations). As with the programming instructions above, calibration does not begin until entry of the Run-Test/
Idle state. The completion of the calibration is not dependent, however, on any further TAP control. This means the
state of the TAP can be returned immediately to the Test-Logic-Reset state. The only consideration would be to not
clock the TAP during critical analog operations. The
fi
rst several milliseconds of the calibration routine are con-
sumed waiting for con
fi
gurations to settle, though, leaving more than enough time to clock the TAP back to the Test-
Logic-Reset state. The bit code for this instruction is shown in Table 5.
The last Lattice instructions are
ABE
and
BBE
(User A or B Bulk Erase). Operation of the device is interrupted dur-
ing an ABE or BBE, during which all inputs are disconnected and all outputs driven to VREF
OUT
(2.5V). To econo-
mize internal circuitry, programming can only be selectively done in one direction (from zeroes to ones). The ABE
MSB
XXXX / 0000 0001 0010 0001 / 0000 0100 001 / 1
LSB
Version
(4 bits)
E
2
Configured
Part Number
(16 bits)
0121h = PAC81
JEDEC Manfacturer
Identity Code for
Lattice Semiconductor
(11 bits)
Constant 1
(1 bit)
per 1149.1-1990
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| ISPPAC81-01SI | In-System Programmable Analog Circuit |
| IT100 | P-CHANNEL JFET SWITCH |
| IT136 | Monolithic Dual PNP General Purpose Amplifier |
| IT136-TO71 | Monolithic Dual PNP General Purpose Amplifier |
| IT137 | Monolithic Dual PNP General Purpose Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC81-01SI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ispPAC-CLK5304S-01T48C | 功能描述:時鐘驅(qū)動器及分配 ISP Zero Delay Unv F an-Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5304S-01T48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5304S-01T48I | 功能描述:時鐘驅(qū)動器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5304S-01T48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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