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參數(shù)資料
| 型號： | ISPPAC81-01PI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 176K |
| 代理商： | ISPPAC81-01PI |
Lattice Semiconductor
ispPAC81 Data Sheet
10
SPI Power-On Condition
The SPI shift register is always reset to all zeroes when an ispPAC81 powers on. That means that if the ENSPI pin
is high at power on, the initial con
fi
guration will be set to a gain of 1X (0dB) and con
fi
guration “A” is selected as the
“wake-up” con
fi
guration. The only way to prevent this behavior would be to hold the ENSPI pin low while applying
power to the device. Because this is usually impractical, it is advised that if the ispPAC81 is used in SPI mode that
it be reloaded to the desired
fi
rst con
fi
guration every time power is cycled to the device and/or that the “A” con
fi
gu-
ration memory hold the desired “wake up”
fi
lter response.
A/B Con
fi
guration
Two complete con
fi
gurations can be stored in the E
2
memory of the ispPAC81. Selection of either the “A” or “B”
con
fi
guration in real time is accomplished with the device in the SPI interface mode (ENSPI pin = logic high). An
eight-bit string is read into the ispPAC81 in the following order: four “don’t care” bits followed by a CAL command
bit, the A/B con
fi
guration setting and gain bits PG2 and PG1.
Table 1. SPI Control Bit Sequence
Table 2. Gain Bit Settings
Table 3. JTAG User Configuration Bits
Bit 7
PG2
Bit 6
PG1
Bit 5
A/B
Bit 4
CAL
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
Gain Setting
1X (0dB)
2X (6dB)
5X (14dB)
10X (20dB)
PG2
0
0
1
1
PG1
0
1
0
1
Symbol
Name
Description
FreqRange Bit
Hi/Lo Frequency Range Bit Depending on the corner frequency, the frequency range bit is automatically set
from within PAC-Designer to optimize the transfer function response of the
ispPAC81. Exists for both the A and B user strings. Can be overridden from
within PAC-Designer from the edit symbol dialog.
User Electronic Signature
These are uncommitted E
2
bits that can be used to store device information for
future reference. The ispPAC81 contains 21 UES bits. These bits are accessible
from within PAC-Designer by using the Edit Symbol, UES Bits command. Part
of user con
fi
guration string A only.
Capacitor Selection Bits
Varying length data words for each of the seven con
fi
guration capacitors of the
ispPAC81. There is a complete set of 70 bits total for each user con
fi
guration
string, A and B.
Initial Con
fi
guration Select With the A/B bit set to “A” (a logic 0), the device will power up in the con
fi
gura-
tion stored in user string A. The designations of A or B would have been deter-
mined initially in the design environment using PAC-Designer. It is also possible
to designate the B user string as the initial or “wake up” con
fi
guration, although
this is not recommended as it blocks the algorithm required to do a “blind” veri-
fi
cation of the A con
fi
guration of a previously programmed device. This is deter-
mined from within PAC-Designer in the edit symbol dialog.
Programmable Gain Bits
Contained only in the A con
fi
guration string. Can also be modi
fi
ed under SPI
control. Refer to Table 2 for bit setting speci
fi
cs.
Electronic Security Fuse
Setting this bit causes all subsequent readouts of the device con
fi
guration to be
disabled (JTAG Verify commands). Can be reset by performing a JTAG user
(USRA) bulk erase commands and reprogramming the device. This feature is
used to prevent unauthorized readout of the device’s con
fi
guration.
UES Bits
Cap Bits
A/B Bit
PG1 & PG2 Bits
ESF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC81-01SI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ispPAC-CLK5304S-01T48C | 功能描述:時(shí)鐘驅(qū)動器及分配 ISP Zero Delay Unv F an-Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5304S-01T48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5304S-01T48I | 功能描述:時(shí)鐘驅(qū)動器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5304S-01T48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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