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參數(shù)資料
| 型號(hào)： | ISPPAC30 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | 在系統(tǒng)可編程模擬電路 |
| 文件頁數(shù)： | 5/30頁 |
| 文件大?。?/td> | 379K |
| 代理商： | ISPPAC30 |
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Lattice Semiconductor
ispPAC30 Preliminary Data Sheet
5
Pin Descriptions
Pins
Symbol
Name
Description
PDIP
SOIC
15, 16, 17, 18,
25, 26, 27, 28
13, 14, 15, 16,
21, 22, 23, 24
IN
Inputs 1, 2, 3, 4 (+ or -)
Plus or Minus
Differential input pins, with two pins per input
(e.g., IN2+ and IN2-). Each are components of
V
IN
, where differential V
IN
= V
IN+
- V
IN-
.
Multiplexer logic input pin. Selects either of two
analog channels to IA1 (instrument ampli
fi
er).
Programmable pull-up, pull-down (default), or
none.
Multiplexer logic input pin. Selects either of two
analog channels to IA4 (instrument ampli
fi
er).
Programmable pull-up, pull-down (default), or
none.
Single-ended output pins. Internal feedback to
inputs accommodated.
Internal voltage reference output pin (+2.5V
nominal). Must be bypassed to GND with a 1
μ
F
capacitor.
Enable SPI logic input pin. When high, causes
serial port to run in SPI mode. Programmable
pull-up or pull-down (default).
Serial interface logic mode select pin (input).
JTAG interface mode only. Internal pull-up.
Serial interface logic pin (output) for both JTAG
and SPI operation modes. Programmable slew
rate, high or low (default).
Serial interface logic pin (input) for both JTAG
and SPI modes. Internal pull-up.
Serial interface logic clock pin (input) for both
JTAG and SPI modes. Programmable pull-up,
pull-down (default), or none.
Chip select logic input pin. SPI data transfer
enabled by this input. Internal pull-up.
Digital pin (input). Commands an auto-calibration
sequence on a rising edge. Internal pull-down.
Power down enable logic pin (input). Shuts down
all power to device. Programmable pull-up
(default), pull-down or none.
Analog supply pin (5V nominal). Should be
bypassed to GND with 1
μ
F and .01
μ
F capaci-
tors.
Ground pin. Should normally be connected to
the analog ground plane.
Analog signal common pin (sense). Always con-
nected to GND. Auto-calibration accuracy is
determined with respect to this pin.
No internal connections are made to these pins
in the PDIP package.
6
5
MSEL1
Multiplexer 1 Control
4
4
MSEL2
Multiplexer 2 Control
21, 22
18, 19
OUT
Outputs 1 and 2
20
17
VREFOUT
Voltage Reference Output
13
11
ENSPI
Enable SPI Mode
12
10
TMS
Test Mode Select
11
9
TDO
Test Data Out
9
8
TDI
Test Data In
8
7
TCK
Test Clock
7
6
CS
Chip Select
3
3
CAL
Auto-Calibrate
2
2
PD
Power Down
14
12
VS
Supply Voltage
1
1
GND
Ground
23
20
SCOM
Signal Common
5, 10, 19, 24
—
NC
No Connects
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC30-01P | In-System Programmable Analog Circuit |
| ISPPAC30-01PI | In-System Programmable Analog Circuit |
| ISPPAC30-01S | In-System Programmable Analog Circuit |
| ISPPAC30-01SI | In-System Programmable Analog Circuit |
| ISPPAC80-01PI | In-System Programmable Analog Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC30-01P | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC30-01PI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC30-01S | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC30-01SI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC80-01PI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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