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參數(shù)資料
| 型號(hào)： | ISPPAC30 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | 在系統(tǒng)可編程模擬電路 |
| 文件頁數(shù)： | 25/30頁 |
| 文件大?。?/td> | 379K |
| 代理商： | ISPPAC30 |
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Lattice Semiconductor
ispPAC30 Preliminary Data Sheet
25
There are no boundary scan logic cells in the ispPAC30 architecture. This does not prevent the ispPAC30 from
functioning correctly, however, when placed in a valid serial chain with other IEEE 1149.1 compliant devices.
A brief description of the ispPAC30 JTAG interface follows. For complete details of the reference speci
fi
cation, refer
to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990 (which now
includes IEEE Std 1149.1a-1993). For complete documentation on how to use ispPAC30 in an embedded serial
interface control environment using the SPI protocol, please refer to application note AN6027,
Using SPI to Config-
ure and Control the ispPAC30
.
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the
ispPAC30. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct sequence,
instructions are shifted into an instruction register which then determines subsequent data input, data output, and
related operations. Device programming is performed by addressing the con
fi
guration register, shifting data in, and
then executing a program con
fi
guration instruction, after which the data is transferred to internal E
2
CMOS cells. It is
these non-volatile cells that store the con
fi
guration or the ispPAC30. A separate set of SRAM registers are pre-
loaded at turn-on and determine the con
fi
guration of the ispPAC30 while it is under power. By cycling the TAP con-
troller through the necessary states, data can also be shifted out of the con
fi
guration register to verify the current
ispPAC30 con
fi
guration in the control SRAM or of the stored E
2
con
fi
guration memory. Instructions exist to access
all data registers and perform other internal control operations.
For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 speci
fi
cation.
Others are functionally speci
fi
ed, but inclusion is strictly optional. Finally, there are provisions for optional data reg-
isters de
fi
ned by the manufacturer. The two required registers are the bypass and boundary-scan registers. For
ispPAC30, the bypass register is a 1-bit shift register that provides a short path through the device when boundary
testing or other operations are not being performed. The ispPAC30, as mentioned, has no boundary scan logic and
therefore no boundary scan register. All instructions relating to boundary scan operations place the ispPAC30 in
the BYPASS mode to maintain compliance with the speci
fi
cation. The optional identi
fi
cation register described in
IEEE 1149.1 is also included in the ispPAC30.
Two additional data registers are included in the TAP of the ispPAC30 are the Lattice de
fi
ned CFG/CFGQ (con
fi
gu-
ration and quick con
fi
guration) and UES (user electronic signature) registers. Figure 9 shows how the instruction
and various data registers are placed in an ispPAC30.
Figure 9. TAP Registers
TDI
TDO
TCK
TMS
CFG/CFGQ REGISTER (112/40 bits)
IDCODE REGISTER (32 bits)
BYPASS REGISTER (1 bit)
INSTRUCTION REGISTER (6 bits)
TEST ACCESS PORT
(TAP) LOGIC
OUTPUT
LATCH
UES REGISTER (16 bits)
M
E2 NON-VOLATILE MEMORY
SRAM DEVICE CONFIGURATION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC30-01P | In-System Programmable Analog Circuit |
| ISPPAC30-01PI | In-System Programmable Analog Circuit |
| ISPPAC30-01S | In-System Programmable Analog Circuit |
| ISPPAC30-01SI | In-System Programmable Analog Circuit |
| ISPPAC80-01PI | In-System Programmable Analog Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC30-01P | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC30-01PI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC30-01S | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC30-01SI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC80-01PI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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