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參數(shù)資料
| 型號(hào)： | ISPPAC20 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | 在系統(tǒng)可編程模擬電路 |
| 文件頁數(shù)： | 31/32頁 |
| 文件大小： | 525K |
| 代理商： | ISPPAC20 |
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Specifications
ispPAC20
31
IEEE Standard 1149.1 Interface
except that they only affect the contents of the DAC
register. The bit codes for these instructions are shown in
Table 6.
ENCAL
(enable calibration) is a Lattice instruction that
enables the start of an auto-calibration sequence. This
operation causes all outputs of the device to go to 0V until
the calibration sequence is completed (see timing speci-
fications). As with the programming instructions above,
calibration does not begin until entry of the Run-Test/Idle
state. The completion of the calibration is not dependent,
however, on any further TAP control. This means the
state of the TAP can be returned immediately to the Test-
Logic-Reset state. The only consideration would be to
not clock the TAP during critical analog operations. The
first several milliseconds of the calibration routine are
consumed waiting for configurations to settle, though,
leaving more than enough time to clock the TAP back to
the Test-Logic-Reset state. The bit code for this instruc-
tion is shown in Table 6.
The last Lattice instruction is
UBE
(user bulk erase).
Operation of the device is interrupted during UBE, after
which all inputs are disconnected and all outputs driven
to V
COM
(2.5V). To economize internal circuitry, pro-
gramming can only be selectively done in one direction
(from zeroes to ones). The UBE is used to return all user
bits to a zero state at the same time. A UBE usually
proceeds a PRGUSR operation, otherwise one to zero
changes would not be implemented. It can also be used
to erase all configuration information from a device and
is the default condition of parts shipped from the factory.
The same programming constraints apply to UBE as for
PRGUSR. The bit code for this instruction is shown in
Table 6.
The ADDUSR, BYPASS, EXTEST, IDCODE and
SAMPLE/PRELOAD instructions are all executed in the
Update-IR state. Other instructions: PRGUSR, VERUSR
and UBE are executed upon entry of the Run-Test/Idle
state.
It is recommended that when all serial interface opera-
tions are completed, the TAP controller be reset and left
in the Test-Logic-Reset state (the power-up default) and
the TCK and TMS inputs idled. This will insure the best
analog performance possible by minimizing the effects of
digital logic
“
feed-through.
”
相關(guān)PDF資料 |
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| ISPPAC20-01J | In-System Programmable Analog Circuit |
| ISPPAC20-01JI | In-System Programmable Analog Circuit |
| ISPPAC30 | In-System Programmable Analog Circuit |
| ISPPAC30-01P | In-System Programmable Analog Circuit |
| ISPPAC30-01PI | In-System Programmable Analog Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC20-01J | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC20-01JI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC20-01TI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC30 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC30-01P | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
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