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參數(shù)資料
| 型號： | ISPPAC20 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | 在系統(tǒng)可編程模擬電路 |
| 文件頁數(shù)： | 27/32頁 |
| 文件大小： | 525K |
| 代理商： | ISPPAC20 |
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Specifications
ispPAC20
27
In-System Programmability
Electronic Security
An electronic security
“
fuse
”
(ESF) bit is provided in every
ispPAC20 device to prevent unauthorized readout of the
E
2
CMOS user bit patterns. Once programmed, this cell
prevents further access to the functional user bits in the
device. This cell can only be erased by reprogramming
the device, so the original configuration can not be
examined once programmed. Usage of this feature is
optional.
Production Programming Support
Once a final configuration is determined, an ASCII format
JEDEC file is created using the PAC-Designer software.
Parts can then be ordered through the usual supply
channels with the user
’
s specific configuration already
preloaded into the parts. PAC-Designer will also export
an SVF file which can be used with ispVM
for embed-
ded programming applications. By virtue of its standard
interface, compatibility is maintained with existing pro-
duction programming equipment giving customers a wide
degree of freedom and flexibility in production planning.
Other options exist for production programming, includ-
ing a C-coded library of ispVM functions. Contact
ispPACs@latticesemi.com for more details.
Evaluation Fixture
Included in the basic ispPAC20 Design Kit is an engineer-
ing prototype board that is connected to the parallel port
of a PC. It demonstrates proper layout techniques for the
ispPAC20 and can be used in real time to check circuit
operation as part of the design process. Input and output
connections as well as a
“
breadboard
”
circuit area are
provided to speed debugging of the circuit.
User Electronic Signature
A user electronic signature (UES) feature is included in
the E
2
memory of the ispPAC20. It contains seven bits
that can be configured by the user to store unique data
such as ID codes, revision numbers or inventory control
data.
Figure 15. Configuring the ispPAC20
“
In-System
”
from a PC Parallel Port
ispDownload
Cable (6')
4
Other
System
Circuitry
ispPAC20
Device
PAC-Designer
Software
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC20-01J | In-System Programmable Analog Circuit |
| ISPPAC20-01JI | In-System Programmable Analog Circuit |
| ISPPAC30 | In-System Programmable Analog Circuit |
| ISPPAC30-01P | In-System Programmable Analog Circuit |
| ISPPAC30-01PI | In-System Programmable Analog Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC20-01J | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC20-01JI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC20-01TI | 功能描述:SPLD - 簡單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC30 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC30-01P | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
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