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參數(shù)資料
| 型號(hào)： | ISPPAC20 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | 在系統(tǒng)可編程模擬電路 |
| 文件頁(yè)數(shù)： | 20/32頁(yè) |
| 文件大?。?/td> | 525K |
| 代理商： | ISPPAC20 |
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Specifications
ispPAC20
20
Theory of Operation (Continued)
Figure 12. ispPAC20 DAC Interface Options
TDO
TDI
DAC
Inputs
Serial DAC Input Shift
Register (SR)
DAC Address
E
2
CMOS Memory
Parallel Input Data Latches
(pre-set to 80h at power-up)
Serial Input Data Latches
(pre-set to 80h at power-up)
3
CS(5)
CS
Registers updated after JTAG command(s):
(1) DBE, PrgDAC (DMode=1)
(2) AddDAC, DBE, PrgDAC (DMode=0)
(3) VerDAC
(4) AddDAC (E
2
bit DSthru=1, ENSPI=0)
SPI mode only: Rising edge of CS
(5) Rising edge of CS (only if DMode=1)
DAC Parallel Input Data Pins D0-D7
ENSPI Input Pin
A
M
DMode Input Pin
DSthru E
2
Bit*
*Decoded from the user selection in the DAC port configuration pop-up.
TCK
Parallel
JTAG/Direct & SPI
JTAG/E
2
(1)
(2)
(3)
(4)
JTAG/E
2
Parallel
JTAG/Direct
SPI
Address
Mode
ENSPI
Pin
0
0
0
1
DSthru
E
2
Bit
0
0
1
X
DMode
Pin
0
1
X
X
Action
JTAG/E
2
Serial Mode
Serial Input SR
E
2
CMOS Memory
Parallel Mode
Parallel Latches
Parallel Latches
JTAG/Direct Serial Mode
Serial Input SR
Serial Latch
SPI Serial Mode
No E
2
Access
Serial Latch
E
2
Cells Programmed Via:
DAC Input Comes From:
DAC Updated On:
During Update-DR,
falling edge TCK (1)
Rising Edge CS
During Update-DR,
falling edge TCK
Rising Edge CS
Rising Edge CS Updates:
Serial Latch
Serial Latch
Parallel Latch
Serial Latch
Serial Latch
DAC Output at Power-Up:
Stored E
2
Value
If E2 bit DisTDO =1,
Otherwise active during
Shift-DR/IR JTAG state
80h (Vout+, Vout-=2.5V) 80h (Vout+, Vout-=2.5V) 80h (Vout+, Vout-=2.5V)
TDO Serial Output in
Hi-Z State During JTAG
AddDAC Operation
No TDO if TCK pin
is not clocked
If E
2
bit DisTDO =1,
Otherwise active during
Shift-DR/IR JTAG state
When CS is high
Notes: (1) DAC output goes from
–
FS to +FS during E
2
programming cycle (JTAG DBE or DAC Bulk Erase, and PrgDAC or Program DAC
commands) before settling to the final input code value.
Table 3. DAC Address Modes
相關(guān)PDF資料 |
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| ISPPAC20-01J | In-System Programmable Analog Circuit |
| ISPPAC20-01JI | In-System Programmable Analog Circuit |
| ISPPAC30 | In-System Programmable Analog Circuit |
| ISPPAC30-01P | In-System Programmable Analog Circuit |
| ISPPAC30-01PI | In-System Programmable Analog Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC20-01J | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC20-01JI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC20-01TI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC30 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC30-01P | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
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