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參數(shù)資料
| 型號： | ISPPAC20 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | 在系統(tǒng)可編程模擬電路 |
| 文件頁數(shù)： | 23/32頁 |
| 文件大?。?/td> | 525K |
| 代理商： | ISPPAC20 |
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Specifications
ispPAC20
23
Theory of Operation (Continued)
IA4 Slew-Rate Enhancement
Because of the special applications addressed by the
inclusion of a polarity control function in IA4, its circuitry
has been modified to include a slew-rate enhancement
feature. This circuitry is not part of the output amplifier
(OA) PACell and therefore does not change the specified
slew rate as given in the data sheet. Rather, it enhances
the operation of IA4 and improves its performance in
applications such as a voltage controlled oscillators
(VCO), thereby improving its performance in reproducing
non-linear transfer functions. The ispPAC is shipped with
this bit normally enabled. If identical operation between
all IA PACells is desired, the SRE bit associated with IA4
can be disabled by selecting the appropriated edit sym-
bol command in PAC-Designer and making the change.
Multiplexer Input control of IA1
An external multiplexer select (MSEL) pin is provided that
controls which of two possible input connections are
routed to the input of IA1. When MSEL is a logic 0, input
line
“
A
”
is selected to go to IA1, when it is a logic 1, input
line
“
B
”
is used. This arrangement allows a number of
applications to be implemented, from something as
straight forward as two input signal channels, to more
complex functions such as those provided for by the
polarity control pin (with the option of different signals
being used as well).
Table 4. Comparator Logic Control Modes/Options
Mode
PC Pin Function
Description
Fixed, Non-Inverting
None (internal).
Always generates a +1 times whatever the gain setting of IA4 is. IA4
can be set to gains of -1 to -10 in this mode. Display of the gain setting
for IA4 in PAC-Designer is of the correct polarity.
IA4 gain setting is correct as shown in PAC-Designer (-1 to -10) if PC
pin input equals a logic 1 (no inversion). If the PC pin input equals a
logic 0, the setting of IA4 will be inverted with respect to what is
displayed in PAC-Designer. Terminating the PC pin low (externally)
in this mode is the most direct way of achieving a constant setting of
positive gain (+1 to +10) for IA4.
Both comparators combine to generate a set/reset function on the
WINDOW logic output pin instead of the usual XOR function. This
signal is also routed internally to IA4 for polarity control. When PC is
a logic 0, CP1 positive transitions generate a set command and
positive transitions of CP2 a reset command. For example, if PACblock
2 is configured as an integrator and its output is fed to CP1 and CP2
(configured for window comparison), a voltage controlled oscillator
will result from the RS Flip-Flop set/reset reversing the polarity every
time the integration exceeds the upper and then lower window
boundaries in sequence. When PC is a logic 1, the output of OA2
goes immediately to 2.5V and stays in
“
hold
”
mode until PC returns
to a logic 0. This effectively implements a gated oscillator function.
In this mode, the output of comparator 1 (CP1) controls the polarity
of IA4, a logic 1 = no inversion, a logic 0 = inverted. When the output
of CP1 is in the direct mode, the polarity control is all internal. If the
CP1 Buffer E2 bit is set, CP1 changes can only occur if clocked by
logic 1 = no inversion (internal). the PC pin externally (rising edge).
Clocks CP1 data register
Always enabled anytime the CP1Buffer E2 configuration bit is set.
(external).
Each rising edge of PC clocks whatever data is read from CP1
’
s
output into its output register regardless of what other function is
being performed by the PC pin. In certain modes listed above, the
operation of CP1 in buffered mode combined with the need to clock
its output using the PC pin, would interfere with or prevent the proper
operation of some circuit function implementations.
PC Direct
Direct control of IA4
polarity via the PC pin,
logic 0 = inverted,
logic 1 = no inversion
(external).
RS Flip-Flop
Clamps OA2 to VREFout
when PC is a logic 1, and
has no effect when it
’
s a
logic 0 (external).
CP1 Direct
None.
IA4 polarity control based
directly on CP1 output, a
logic 0 = inverted,
PC Clock
相關PDF資料 |
PDF描述 |
|---|---|
| ISPPAC20-01J | In-System Programmable Analog Circuit |
| ISPPAC20-01JI | In-System Programmable Analog Circuit |
| ISPPAC30 | In-System Programmable Analog Circuit |
| ISPPAC30-01P | In-System Programmable Analog Circuit |
| ISPPAC30-01PI | In-System Programmable Analog Circuit |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC20-01J | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC20-01JI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC20-01TI | 功能描述:SPLD - 簡單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC30 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC30-01P | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
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