參數(shù)資料
型號： ISPPAC20-01JI
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 模擬信號調(diào)理
英文描述： In-System Programmable Analog Circuit
中文描述： SPECIALTY ANALOG CIRCUIT, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 8/32頁
文件大?。?/td> 525K
代理商： ISPPAC20-01JI
Specifications
ispPAC20
8
39, 6, 23
1,12,29
GND
Ground
Ground pins. All should normally be connected to same analog ground
plane.
Common-mode voltage reference output pin (+2.5V nominal). Must be
bypassed to GND with a 1
μ
F capacitor.
Multiplexer logic input pin. Selects either of two analog channels to
one of the PACblock inputs. Input A selected when low, B when high.
Internal pull-down to GND.
Enable SPI logic input pin. When high, causes serial port to run in SPI
mode. Internal pull-down to GND.
Factory Test pin. Connect to GND for proper circuit operation.
Differential input pins, with two pins per input (e.g., IN2+ and IN2-).
components of V
IN
, where differential V
IN
= V
IN+
- V
IN-
.
Differential output pins, with two pins per output (e.g., OUT2+ and
OUT2-). Complementary with respect to VREF
OUT
, where differential
V
OUT
= V
OUT+
- V
OUT-
.
Analog supply voltage pins (5V nominal). Must all be connected
together. Should all be bypassed to GND with 1
μ
F and .01
μ
F
capacitors.
Serial interface logic pin (input) for both JTAG and SPI modes. Input
data valid on rising edge of TCK (JTAG). Internal pull-up to V
S
.
Serial interface logic mode select pin (input). JTAG interface mode
only. Internal pull-up to V
S
.
Serial interface logic clock pin (input).
Polarity logic input pin. Controls polarity of one PACblock input.
Operation determined by user configuration of device. Internal
pull-down to GND.
Chip select logic input pin. SPI data and DAC parallel interface clock.
Internal pull-up to V
S
.
Serial interface logic pin (output) for both JTAG and SPI operation
modes. Output data valid on falling edge of TCK (JTAG).
DAC mode logic input. When high, DAC can be loaded via the parallel
interface pins D0-D7 using CS as the latch command. Internal pull-
down to GND.
Window comparison logic pin (output). Configured by user to
Comparator Outperform comparator logic functions.
Comparator logic pins (outputs). One pin for logic level of each
comparator.
Differential input pins, CPIN+ and CPIN-. Plus and minus components
of V
IN
, where differential CP
IN
= CP
IN+
- CP
IN-
.
DAC data pins (inputs). Eight parallel inputs to DAC. Clocked
by CS pin. D0 is the LSB and D7 is the MSB.
Differential output pins (DOUT+ and DOUT-). Complementary with
respect to VREFout, where differential D
OUT
= D
OUT+
- D
OUT-
.
Input pin for optional analog Common Mode Output Voltage (CMVin).
Replaces VREFout (+2.5V) with this voltage for any user-selected
PACblock.
Digital pin (input). Commands an auto-calibration sequence on
a rising edge. Internal pull-down to GND.
40
2
VREFout
Common-Mode
Reference
Multiplexer Control
43
5
MSEL
42
4
ENSPI
Enable SPI Mode
41
3
TEST
IN
Factory Test pin
Inputs 1, 2, 3 (+ or -)
Plus or minus
Outputs 1,2 (+ or -)
44, 1, 2,
3, 9, 10
4, 5,
7, 8
6, 7, 8, 9,
15, 16
10, 11,
13, 14
OUT
11, 19, 34
17, 25, 40
VS
Supply Voltage
12
18
TDI
Test Data In
13
19
TMS
Test Mode Select
14
15
20
21
TCK
PC
Test Clock
Polarity Control
16
22
CS
Chip Select
17
23
TDO
Test Data Out
18
24
DMODE
DAC Mode Select
20
26
WINDOW
Window
21, 22
27, 28
CPOUT
Comparator
Outputs
Comparator Inputs
24, 25
30, 31
CPIN
26 to 33
32 to 39
D0 to D7
DAC Data Inputs
35, 36
41, 42
DACOUT
DAC Outputs
(+ or -)
Input for
Optional VREFOUT
37
43
CMVin
38
44
CAL
Auto-Calibrate
Pin Descriptions
TQFP
PLCC
Symbol
Name
Description
Pin(s)
Connection Notes
1.
All inputs and outputs are labeled with plus (+) and minus (-) signs. Polarity is labeled for reference and can be selected externally by
reversing pin connections or internally under user programmable control.
2.
All analog output pins are
“
hard-wired
”
to internal output devices and should be left open if not used. Outputs of uncommitted PACblocks
are forced to VREF
OUT
(2.5V) and can be used as low impedance reference output buffers. V
OUT+
and V
OUT-
should not be tied together
as unnecessary power will be dissipated.
3.
When the signal input is single-ended, the other half of the unused differential input must be connected to a DC common-mode reference
(usually VREF
OUT
, 2.5V).
相關PDF資料
PDF描述
ISPPAC30 In-System Programmable Analog Circuit
ISPPAC30-01P In-System Programmable Analog Circuit
ISPPAC30-01PI In-System Programmable Analog Circuit
ISPPAC30-01S In-System Programmable Analog Circuit
ISPPAC30-01SI In-System Programmable Analog Circuit
相關代理商/技術參數(shù)
參數(shù)描述
ISPPAC20-01TI 功能描述:SPLD - 簡單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
ISPPAC30 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit
ISPPAC30-01P 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit
ISPPAC30-01PI 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
ISPPAC30-01S 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit
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