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參數(shù)資料
| 型號： | ISPPAC20-01JI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 2/32頁 |
| 文件大?。?/td> | 525K |
| 代理商： | ISPPAC20-01JI |
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Specifications
ispPAC20
2
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
MAX. UNITS
PACblock Analog Input
V
IN
±
(1)
V
IN-DIFF
V
OS
(2)
Input Voltage Range
Differential Input Voltage Swing (2)
Differential Offset Voltage (Input Referred)
Applied to Either V
IN+
or V
IN
–
2| V
IN+
–
V
IN
–
|
G = 10
G = 1
-40 to +85
°
C
1
6
4
V
V
p-p
μ
V
mV
μ
V/
°
C
pF
pA
nV/
√
Hz
20
0.2
50
10
9
2
3
38
100
1.0
V
OS
/
T
R
IN
C
IN
I
B
e
N
PACblock Analog Output
V
OUT
±
V
OUT-DIFF
I
OUT
±
V
CM
PACblock Static Performance
G
Differential Offset Voltage Drift
Input Resistance
Input Capacitance
Input Bias Current
Input Noise Voltage Density
at DC
At 10kHz, Referred to Input, G = 10
Output Voltage Range
Differential Output Voltage Swing (2)
Output Current
Common Mode Output Voltage
Present at Either V
OUT+
or V
OUT
–
2| V
OUT+
–
V
OUT
–
|
Source/Sink
(V
OUT+
+ V
OUT-
)/2 ; V
IN+
= V
IN
–
0.1
9.6
10
2.475
4.9
V
V
p-p
mA
V
2.500
2.525
Programmable Gain Range
Gain Error
Gain Matching
Gain Drift
Power Supply Rejection
Each individual PACblock
R
L
= 300
Differential
Between Two Inputs of Same PACblock
-40 to +85
°
C
Differential at 1kHz
Single-ended at 1kHz
0
26
4.0
3.0
dB
%
%
G
/
T
PSR
20
80
77
ppm/
°
C
dB
dB
Common Mode Reference Output (VREF
OUT
)
VREF
OUT
Output Voltage Range
CMV
IN
(4)
Common Mode Output Voltage Input
Output Voltage Drift
IREF
OUT
Nominally 2.500V
-0.2
1.25
+0.2
3.25
%
V
Optional External VREF
OUT
Reference Voltage
-40 to +85
°
C
Source
Sink
10MHz Bandwidth; 1
μ
F Bypass Capacitor
1kHz
50
50
350
40
80
ppm/
°
C
μ
A
μ
A
μ
V
RMS
dB
Output Current
Output Noise Voltage
Power Supply Rejection
Digital-to-Analog Converter (DAC) PACell
Resolution
8
bits
lsb
lsb
%
INL
DNL
Integral Non-Linearity Error
Differential Non-Linearity
Gain Error
Gain Drift
Differential Offset Voltage
Common Mode Output Voltage
Power Supply Rejection
Differential Offset Voltage Drift
Differential Full Scale Range
Voltage Output Range
Output Current
Output Slew Rate
Output Settling Time 0.1%
Temperature Range
±
0.5
±
1.0
2.5
Guaranteed Monotonic
/
T
V
OS
V
CM
PSR
V
OS
/
T
FSR
V
OUT
±
I
OUT
±
SR
t
S
-40 to +85
°
C
20
ppm/
°
C
mV
V
dB
μ
V/
°
C
V
V
mA
V/
μ
s
μ
s
2
(D
OUT+
+ D
OUT-
)/2
Differential at 1kHz
-40 to +85
°
C
DAC Code 00h to FFh
R
L
= 1K
Differential
Source/Sink
2.495
2.500
80
50
6.0
2.505
1
10
4
1.3
4.8
6V
DIFF
Input Step
6.0
Operation
Storage
-40
-65
+85
+150
°
C
°
C
DC Electrical Characteristics
T
A
= 25
°
C; V
S
= 5.0V; Signal path = V
IN
to V
OUT
of one PACblock (second input unused); 1V
≤
V
OUT
≤
4V; Gain = 1; Output load
= 200pf, 1M
. Feedback enabled; Feedback capacitor = minimum; Auto-cal initiated immediately prior. (Unless otherwise specified).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC20-01TI | 功能描述:SPLD - 簡單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC30 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC30-01P | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC30-01PI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC30-01S | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
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