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參數(shù)資料
| 型號(hào)： | ISPPAC20-01JI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 525K |
| 代理商： | ISPPAC20-01JI |
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Specifications
ispPAC20
19
Theory of Operation (Continued)
DAC PACell
The ispPAC20 contains an 8-bit, voltage output, digital-
to-analog converter (DAC) PACell with many unique
features and options. Interface modes are user select-
able and include a direct 8-bit parallel port, a serial JTAG
address mode, or serial SPI address mode. The output of
the DAC is fully differential, making it compatible with the
rest of the ispPAC20
’
s internal analog I/O. The DAC
’
s
voltage output is available via external pins as well as by
on-chip routing for optional internal connection to either
the comparator PACells or any of the instrument amplifier
input PACells.
DAC Data Input Coding
Data input to the DAC, whether in serial or parallel mode,
determines its output value. The coding of the DAC is in
straight binary and corresponds to input to output rela-
tionship shown in Table 2, DAC I/O. In all serial modes,
8 bits of data are clocked in with D0 (the LSB) being first
in the data stream and D7 (the MSB) being last.
DAC Address Modes
Addressing modes are controlled from within
PAC-Designer (options in the DAC port configuration
pop-up) and by two external pins (DMode and ENSPI).
Figure 12 diagrams the various input data paths used to
implement the various ispPAC20 DAC addressing modes.
Also included in the figure is a truth table of the user E
2
settings and input logic levels required to enable them. All
serial data input modes are 8 bits long and clocked in LSB
(D0) first.
The choice of addressing modes depends largely on
application needs, but the primary benefit of each ad-
dressing mode is as follows:
JTAG/E
2
: Power-up state of DAC is determined by E
2
configuration memory. The DAC input code can still be
changed, but only by reprogramming the E
2
memory via
JTAG command and subject to the maximum number of
programming cycles allowed. This is the preferred mode
to use when the DAC setting must be retained when
device power has been cycled off and then on again.
Parallel
: This mode allows direct parallel update access
to the DAC. The DAC can be updated continuously
without affecting E
2
programming cycle endurance is-
sues. The DAC E
2
configuration cells can still be
programmed via serial JTAG commands directly from the
value stored in the parallel input data latches at any time,
if desired.
JTAG/Direct
: The DAC can be addressed directly, by-
passing the E
2
configuration memory via the standard
JTAG serial interface protocol. Using this serial address-
ing mode retains the ability to reprogram the ispPAC20
DAC at any time without having to reconfigure the inter-
face from one mode to another.
SPI
: The DAC can be addressed directly, bypassing the
E
2
configuration memory via an SPI compatible serial
interface protocol. The SPI serial interface is one of the
most widely used protocols for communication with mixed
signal devices of all types. While in the SPI addressing
mode, programming of the DAC E
2
configuration memory
is not possible.
Table 2. DAC I/O
Code
Nominal Voltage
Vout+ (V)
1.0000
1.3750
1.7500
2.1250
2.4883
2.5000
2.5117
2.8750
3.2500
3.6250
3.9883
x + 0.0117
4.0000
DEC
0
32
64
96
127
128
129
160
192
224
255
HEX
00
20
40
60
7F
80
81
A0
C0
E0
FF
Vout- (V)
4.0000
3.6250
3.2500
2.8750
2.5117
2.5000
2.4883
2.1250
1.7500
1.3750
1.0117
x - 0.0117
1.0000
Vout (Vdiff)
-3.0000
-2.2500
-1.5000
-0.7500
-0.0234
0.0000
0.0234
0.7500
1.5000
2.2500
2.9766
0.0234
2.9766
-Full Scale (-FS)
Mid Scale (MS)
MS + 1LSB
MS - 1LSB
+Full Scale (+FS)
LSB Step Size
+FS + 1LSB
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相關(guān)代理商/技術(shù)參數(shù) |
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| ISPPAC20-01TI | 功能描述:SPLD - 簡單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC30 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC30-01P | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
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| ISPPAC30-01S | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
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