參數(shù)資料
型號： ISPPAC20-01JI
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 模擬信號調(diào)理
英文描述： In-System Programmable Analog Circuit
中文描述： SPECIALTY ANALOG CIRCUIT, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 5/32頁
文件大?。?/td> 525K
代理商： ISPPAC20-01JI
Specifications
ispPAC20
5
Timing Specifications (JTAG Interface Mode)
T
A
= 25
°
C; V
S
= +5.0V (Unless otherwise specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNITS
Dynamic Performance
tckmin
tckh
tckl
tmss
tmsh
tdis
tdih
tdozx
tdov
tdoxz
tpwp
tpwe
tpwcal1
tcalmin
tpwcal2
Minimum Clock Period
TCK High Time
TCK Low Time
TMS Setup Time
TMS Hold Time
TDI Setup Time
TDI Hold Time
TDO Float to Valid Delay
TDO Valid Delay
TDO Valid to Float Delay
Time for a programming operation
Time for an erase operation
Time for auto-cal operation on power-up
Minimum auto-cal pulse width
Time for user initiated auto-cal operation
200
50
50
15
10
15
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
ns
ms
60
60
60
100
100
250
Executed in Run-Test/Idle
Executed in Run-Test/Idle
Automatically executed at power-up
80
80
40
Executed on rising edge of CAL
100
tckmin
tckh
tckl
tmss
tdis
tmsh
tdih
tdozx
tdov
tdoxz
TCK
TMS
TDI
TDO
tmss
tmss
TCK
TMS
tpwp, tpwe
*(PRGUSR/UBE executed in
Run-Test/Idle state)
CAL
(Note: CAL internally
initiated at device turn-on.)
V
OUT+
= V
OUT
–
= 0
VOUT
tpwcal1, tpwcal2
tcalmin
*Note: During device JTAG programming, filsum PACblock analog outputs will stop responding to normal input stimulus. This
is because all configuration information is erased and then re-written as part of a normal programming cycle, momentarily
disrupting the input to output signal path. Behavior is not predictable during either of these steps since the analog outputs are
not clamped during a programming cycle. Usually, however, the outputs will slew to either 0V (Ground) or 5V (V
supply
) or 2.5V
(VREF
OUT
). This behavior is partially determined by conditions existing immediately prior to device reprogramming and
intermediate configurations that occur during the process. DAC outputs will go to -FS (-3V
DIFF
) during bulk erase and then to
+FS (+3V
DIFF
) for less than 2ms during final programming before assuming the programmed code value. Comparator outputs
can change due to a number of additional factors and are therefore not predictable until the final device configuration is
reached. Also, any configuration of the comparators that modifies their mode of operation (e.g., hysteresis on, clocked output
mode, etc) can alter output states from initial settings until additional external conditions are reapplied to the device.
相關(guān)PDF資料
PDF描述
ISPPAC30 In-System Programmable Analog Circuit
ISPPAC30-01P In-System Programmable Analog Circuit
ISPPAC30-01PI In-System Programmable Analog Circuit
ISPPAC30-01S In-System Programmable Analog Circuit
ISPPAC30-01SI In-System Programmable Analog Circuit
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPAC20-01TI 功能描述:SPLD - 簡單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
ISPPAC30 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit
ISPPAC30-01P 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit
ISPPAC30-01PI 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
ISPPAC30-01S 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit
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