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參數(shù)資料
| 型號(hào)： | ISPPAC10-01SI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁(yè)數(shù)： | 5/23頁(yè) |
| 文件大?。?/td> | 415K |
| 代理商： | ISPPAC10-01SI |
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Specifications
ispPAC10
5
Pin
Symbol
Name
Description
1
OUT2+
Output 2(+)
Differential output pin, V
OUT
+
. (Plus complement of V
OUT
with respect to VREF
OUT
,
where differential V
OUT
= V
OUT
+
- V
OUT
-
).
Differential output pin, V
OUT
-
. (Minus component, where differential V
OUT
= V
OUT
+
- V
OUT
-
).
Differential input pin, V
IN
+
. (Plus V
IN
, where differential V
IN
= V
IN
+
- V
IN
-
).
Differential input pin, V
IN
-
. (Minus component of differential V
IN
, where V
IN
= V
IN
+
- V
IN
-
).
Serial interface logic input pin. Input data valid on rising edge of TCK.
Serial interface logic reset pin (input). Asynchronously resets logic controller. Active low.
Reset is equivalent of power-on default.
Analog supply voltage pin (5V nominal).
Should be bypassed to GND with 1
μ
F and .01
μ
F capacitors.
Serial interface logic output pin. Input data valid on falling edge of TCK.
Serial interface logic clock pin (input). Best analog performance when TCK is idle.
Serial interface logic mode select pin (input).
Differential input pin, V
IN
-
Differential input pin, V
IN
+
Differential output pin, V
OUT
-
Differential output pin, V
OUT
+
Differential output pin, V
OUT
+
Differential output pin, V
OUT
-
Differential input pin, V
IN
+
Differential input pin, V
IN
-
Input pin for optional (external) analog Common-Mode Voltage (V
CM
). Replaces VREF
OUT
(+2.5V) for any so programmed PACblock as its common-mode output voltage value.
Digital input pin. Commands an auto-calibration sequence on a rising edge.
Ground pin. Should normally be connected to analog ground plane.
Common-mode voltage reference output pin (+2.5V nominal). Must be bypassed to GND
with a 0.1
μ
F capacitor.
Manufacturing test pin. Connect to GND for proper circuit operation.
Manufacturing test pin. Connect to GND for proper circuit operation.
Differential input pin, V
IN
-
Differential input pin, V
IN
+
Differential output pin, V
OUT
-
Differential output pin, V
OUT
+
2
3
4
5
6
OUT2-
IN2+
IN2-
TDI
TRST
Output 2(-)
Input 2(+)
Input 2(-)
Test Data In
Test Reset
7
VS
Supply Voltage
8
9
10
11
12
13
14
15
16
17
18
19
TDO
TCK
TMS
IN4-
IN4+
OUT4-
OUT4+
OUT3+
OUT3-
IN3+
IN3-
CMV
IN
Test Data Out
Test Clock
Test Mode Select
Input 4(-)
Input 4(+)
Output 4(-)
Output 4(+)
Output 3(+)
Output 3(-)
Input 3(+)
Input 3(-)
Input for V
CM
Reference
20
21
22
CAL
GND
VREF
OUT
Auto-Calibrate
Ground
Common-Mode Reference
23
24
25
26
27
28
TEST
TEST
IN1-
IN1+
OUT1-
OUT1+
Test Pin
Test Pin
Input 1(-)
Input 1(+)
Output 1(-)
Output 1(+)
Pin Descriptions
Connection Notes
1. All inputs and outputs are labeled with plus (+) and
minus (-) signs. Polarity is labeled for reference and
can be selected externally by reversing pin connec-
tions or internally under user programmable control.
2. All analog output pins are
“
hard-wired
”
to internal
output devices and should be left open if not used.
Outputs of uncommitted PACblocks are forced to
VREF
OUT
(2.5V) and can be used as low impedance
reference output buffers. V
OUT+
and V
OUT-
should not
be tied together as unnecessary power will be dissi-
pated.
3. When the signal input is single-ended, the other half of
the unused differential input must be connected to a
DC common-mode reference (usually VREF
OUT
, 2.5V).
OUT2+
OUT2
–
IN2+
IN2
–
OUT1+
OUT1
–
IN1+
IN1
–
TEST (tie to GND)
TEST (tie to GND)
OUT4
–
OUT4+
OUT3
–
OUT3+
IN4
–
IN4+
IN3
–
IN3+
TDI
TDO
TCK
TMS
TRST
VS (5V)
VREFout
GND (0V)
CAL
CMVin
1
i
28-Pin
Top View
Pin Configuration
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| ISPPAC20 | In-System Programmable Analog Circuit |
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|---|---|
| ISPPAC20 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC20-01J | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC20-01JI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC20-01TI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC30 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
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