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參數(shù)資料
| 型號(hào)： | ISPPAC10-01SI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 415K |
| 代理商： | ISPPAC10-01SI |
Specifications
ispPAC10
11
F
OUT
V
m3
OUT
V
m1
IN
sC
))
V
(
(
g
g
V
-
–
+
+
-
+
(3a)
F
OUT
V
m3
OUT
V
m1
IN
sC
))
V
(
(
g
g
V
+
–
+
-
-
(3b)
where V- and V+ are the voltages at the op amp inverting
and non-inverting inputs respectively. Because of feed-
back they are equal, so
)
sC
V
(
g
V
g
V
=
)
sC
V
+
(
g
V
–
g
V
F
OUT
m3
OUT
m1
IN
F
OUT
m3
OUT
m1
IN
-
+
+
+
-
(4)
and the differential output voltage V
OUT
is the difference
V
OUT+
- V
OUT-
,
2
sC
g
g
V
V
F
3
m
1
m
IN
OUT
+
=
(5a)
Since the PACblock has two separate inputs (IA1 and
IA2) summed at the output amplifier input:
2
sC
g
V
g
k
V
g
k
V
F
m3
IN2
m
2
IN1
m
1
OUT
+
+
=
(5b)
The input amplifiers have a programmable gain of
k
·
2
μ
A/V (g
m1
and g
m2
) where k is an integer from -10 to
10. The feedback amplifier transconductance g
m3
is fixed
at 2
μ
A/V, but may be disabled (g
m3
= 0) to open-circuit
the output amplifier
’
s resistive feedback. The program-
mable feedback capacitance lies in the range 1pF to
62pF.
The PACblock model from PAC-Designer is shown in
Figure 4. The output amplifier is configured as an invert-
ing mode op amp and illustrates the summing
configuration. The input instrument amplifiers are shown
to make it clear that unlike a typical inverting op amp, the
PACblock input impedance is extremely high. The input
amplifier (IA) transconductance (gain) is shown as the
value (k) above or below each amplifier. The gain of IA1
and IA2 are independently programmable. Because the
feedback transconductor IAF (designated here as R
F
)
can be disabled by the user, a user configurable switch
is shown in series.
Figure 4. PAC-Designer FilSum PACblock
k
1
C
F
OA1
IA1
IA2
PACblock
2.5V
1pF to 62pF
k
2
Feedback Enable
2
2
Two
Differential
Inputs
Differential
Output
k
N
=
–
1, 2...10
Common-
Mode Voltage
Input
Summation
2
R
F
The FilSum PACblock implements two primary functions:
the lossy integrator (low pass filter) and the integrator,
both with gain.
Lossy ntegrator
. The lossy integrator
’
s schematic within
PAC-Designer is shown in Figure 5. Manipulating the
PACblock transfer function of Equation 5 to better show
the pole frequency yields:
m
F
IN2
V
2
IN1
V
1
OUT
V
g
2
sC
1
k
k
+
+
=
(6)
Figure 5. PAC-Designer PACblock Lossy Integrator
k
1
k
2
V
OUT
V
IN1
V
IN2
C
F
R
F
IA1
IA2
OA1
2.5V
The DC gain of each input is set by k
1
or k
2
respectively,
the gain constant for the input amplifiers. Below the pole
frequency, this circuit can be viewed as a gain block.
Because of the bandwidth trim capacitance, there is a
minimum value of C
F
causing the bandwidth to be ap-
proximately 550kHz when the DC gain is one. For larger
gains, the input amplifier bandwidth begins to dominate
the overall PACblock response, limiting the bandwidth to
about 330kHz when the gain is 10.
Examining this transfer function shows the pole fre-
quency is (1/2
π
)(2g
m
/C). Since g
m
= 2
μ
A/V and 1pF
≤
C
F
≤
62pF, then 600kHz
≥
f
P
≥
10kHz. Due to the selection
options for feedback capacitance, there are at least 120
poles between 10kHz and 100kHz.
Theory of Operation (Continued)
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