參數(shù)資料
型號(hào): ISPPAC10-01SI
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: 模擬信號(hào)調(diào)理
英文描述: In-System Programmable Analog Circuit
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO28
封裝: PLASTIC, SOIC-28
文件頁(yè)數(shù): 16/23頁(yè)
文件大小: 415K
代理商: ISPPAC10-01SI
Specifications
ispPAC10
16
Software-Based Design Environment
Design Entry Software
Designers configure the ispPAC10 and verify its perfor-
mance using PAC-Designer, an easy to use, Microsoft
Windows compatible program. Circuit designs are en-
tered graphically and then verified, all within the
PAC-Designer environment. Full device programming is
supported using PC parallel port I/O operations and a
download cable connected to the serial programming
interface of the ispPAC10. A library of configurations is
included with basic solutions and examples of advanced
circuit techniques. In addition, comprehensive on-line
and printed documentation is provided that covers all
aspects of PAC-Designer operation.
The PAC-Designer schematic window, shown in Figure
12, provides access to all configurable ispPAC10 ele-
ments via its graphical user interface. All analog input
and output pins are represented. Static or non-config-
urable pins such as power, ground, VREF
OUT
, and the
serial digital interface are omitted for clarity. Any element
in the schematic window can be accessed via mouse
operations as well as menu commands. When com-
pleted, configurations can be saved, simulated, and
downloaded to devices.
PAC-Designer operation can be automated and ex-
tended by using custom-designed Visual Basic
programs
that set the interconnections and the parameters of
ispPAC products. These stand-alone programs are called
circuit generator macros. An example of such a macro is
the biquad filter generator supplied with PAC-Designer.
With this macro, filter parameters such as gain, Q and
corner frequency are input directly and then automati-
cally converted to a schematic configuration. The
application example shown in Figure 7b was generated
using the biquad filter generator macro. More information
on this and other topics is included in the on-line docu-
mentation as well as ispPAC application notes.
Figure 12. Initial PAC-Designer Schematic Design Entry Screen
PAC Designer - [Design1]
File Edit View Tools Options Window Help
Ready
OA1
IA1
1
IA2
1
1.07 pF
OA2
IA3
1
IA4
1
1.07 pF
OA3
IA5
1
IA6
1
1.07 pF
OA4
IA7
1
IA8
1
1.07 pF
2.5V
2.5V
2.5V
2.5V
IN1
IN2
IN3
IN4
OUT1
OUT2
OUT3
OUT4
PAC Block 1
PAC Block 2
PAC Block 3
PAC Block 4
UES = 00000000
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