參數(shù)資料
型號(hào)： ISPPAC-POWR1014A-01TN48I
廠(chǎng)商： LATTICE SEMICONDUCTOR CORP
元件分類(lèi)： 電源管理
英文描述： In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
中文描述： 10-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48
封裝： LEAD FREE, TQFP-48
文件頁(yè)數(shù)： 38/45頁(yè)
文件大小： 999K
代理商： ISPPAC-POWR1014A-01TN48I
Lattice Semiconductor
ispPAC-POWR1014/A Data Sheet
38
The optional
IDCODE
(identification code) instruction is incorporated in the ispPAC-POWR1014/A and leaves it in
its functional mode when executed. It selects the Device Identification Register to be connected between TDI and
TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer,
device type and version code (Figure 31). Access to the Identification Register is immediately available, via a TAP
data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this
instruction is defined by Lattice as shown in Table 11.
Figure 31. ispPAC-POWR1014/A ID Code
ispPAC-POWR1014/A Specific Instructions
There are 25 unique instructions specified by Lattice for the ispPAC-POWR1014/A. These instructions are primarily
used to interface to the various user registers and the E
2
CMOS non-volatile memory. Additional instructions are
used to control or monitor other features of the device. A brief description of each unique instruction is provided in
detail below, and the bit codes are found in Table 11.
PLD_ADDRESS_SHIFT
– This instruction is used to set the address of the PLD A
N
D/ARCH arrays for subsequent
program or read operations. This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PLD_DATA_SHIFT
– This instruction is used to shift PLD data into the register prior to programming or reading.
This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PLD_INIT_ADDR_FOR_PROG_INCR
– This instruction prepares the PLD address register for subsequent
PLD_PROG_I
N
CR or PLD_VERIFY_I
N
CR instructions.
PLD_PROG_INCR
– This instruction programs the PLD data register for the current address and increments the
address register for the next set of data.
PLD_PROGRAM
– This instruction programs the selected PLD A
N
D/ARCH array column. The specific column is
preselected by using PLD_ADDRESS_SHIFT instruction. The programming occurs at the second rising edge of
the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_E
N
ABLE
instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PROGRAM_SECURITY
– This instruction is used to program the electronic security fuse (ESF) bit. Programming
the ESF bit protects proprietary designs from being read out. The programming occurs at the second rising edge of
the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_E
N
ABLE
instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PLD_VERIFY
– This instruction is used to read the content of the selected PLD A
N
D/ARCH array column. This
specific column is preselected by using PLD_ADDRESS_SHIFT instruction. This instruction also forces the outputs
into the OUTPUTS_HIGHZ.
DISCHARGE
– This instruction is used to discharge the internal programming supply voltage after an erase or pro-
gramming cycle and prepares ispPAC-POWR1014/A for a read cycle. This instruction also forces the outputs into
the OUTPUTS_HIGHZ.
0000 0000 0001 0100 0101 / 0000 0100 001 / 1
(ispPAC-POWR1014A)
0001 0000 0001 0100 0101 / 0000 0100 001 / 1
(ispPAC-POWR1014)
MSB
LSB
Part
N
umber
(20 bits)
00145h = ispPAC-POWR1014A
10145h = ispPAC-POWR1014
JEDEC Manufacturer
Identity Code for
Lattice Semiconductor
(11 bits)
Constant 1
(1 bit)
per 1149.1-1990
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACPOWR1014A01TN48IAG6 制造商:Lattice Semiconductor Corporation 功能描述:
ispPAC-POWR1014A-02T48I 功能描述:監(jiān)控電路 ispPAC-POWR1014 w/ ADC INDLOG DEV(ECP3) RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類(lèi)型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開(kāi)關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
ispPAC-POWR1014A-02TN48I 功能描述:監(jiān)控電路 ispPAC-POWR1014 w/ ADC, IND, Pb-Free RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類(lèi)型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開(kāi)關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
ISPPACPOWR120801T44E 制造商:Lattice Semiconductor Corporation 功能描述:
ISPPAC-POWR1208-01T44E 功能描述:監(jiān)控電路 PROGRAMMABLE PWR SUPPLY CONTR RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類(lèi)型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開(kāi)關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
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