參數(shù)資料
型號(hào)： ISPPAC-POWR1014A-01TN48I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 電源管理
英文描述： In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
中文描述： 10-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48
封裝： LEAD FREE, TQFP-48
文件頁(yè)數(shù)： 21/45頁(yè)
文件大小： 999K
代理商： ISPPAC-POWR1014A-01TN48I
Lattice Semiconductor
ispPAC-POWR1014/A Data Sheet
21
cuits and ADC. The ispPAC-POWR1014/A can be programmed to operate in three modes: Master mode, Standal-
one mode and Slave mode. Table 5 summarizes the operating modes of ispPAC-POWR1014/A.
Table 5. ispPAC-POWR1014/A Operating Modes
A divide-by-32 prescaler divides the internal 8MHz oscillator (or external clock, if selected) down to 250kHz for the
PLD clock and for the programmable timers. This PLD clock may be made available on the PLDCLK pin by closing
SW2. Each of the four timers provides independent timeout intervals ranging from 32μs to 1.96 seconds in 128
steps.
Digital Outputs
The ispPAC-POWR1014/A provides 14 digital outputs, HVOUT[1:2] and OUT[3:14]. Outputs OUT[3:14] are perma-
nently configured as open drain to provide a high degree of flexibility when interfacing to logic signals, LEDs, opto-
couplers, and power supply control inputs. The HVOUT[1:2] pins can be configured as either high voltage FET driv-
ers or open drain outputs. Each of these outputs may be controlled either from the PLD or from the I
2
C bus (isp-
PAC-POWR1014A only). The determination whether a given output is under PLD or I
2
C control may be made on a
pin-by-pin basis (see Figure 12). For further details on controlling the outputs through I
2
C, please see the I
2
C/
SMBUS Interface section of this data sheet.
Figure 12. Digital Output Pin Configuration
High-Voltage Outputs
In addition to being usable as digital open-drain outputs, the ispPAC-POWR1014/A’s HVOUT1-HVOUT2 output
pins can be programmed to operate as high-voltage FET drivers. Figure 13 shows the details of the HVOUT gate
drivers. Each of these outputs may be controlled from the PLD, or with the ispPAC-POWR1014A, from the I
2
C bus
(see Figure 13). For further details on controlling the outputs through I
2
C, please see the I
2
C/SMBUS Interface sec-
tion of this data sheet.
Timer
Operating Mode
Standalone
SW0
Closed
SW1
Open
Condition
Comments
When only one ispPAC-POWR1014/A is used.
When more than one ispPAC-POWR1014/A is
used in a board, one of them should be configured
to operate in this mode.
When more than one ispPAC-POWR1014/As is
used in a board. Other than the master, the rest of
the ispPAC-POWR1014/As should be pro-
grammed as slaves.
MCLK pin tristated
Master
Closed
Closed
MCLK pin outputs 8MHz clock
Slave
Open
Closed
MCLK pin is input
OUTx
Pin
Digital Control
from PLD
Digital Control from I
2
C Register
(ispPAC-PO
W
R1014A only)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACPOWR1014A01TN48IAG6 制造商:Lattice Semiconductor Corporation 功能描述:
ispPAC-POWR1014A-02T48I 功能描述:監(jiān)控電路 ispPAC-POWR1014 w/ ADC INDLOG DEV(ECP3) RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開(kāi)關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
ispPAC-POWR1014A-02TN48I 功能描述:監(jiān)控電路 ispPAC-POWR1014 w/ ADC, IND, Pb-Free RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開(kāi)關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
ISPPACPOWR120801T44E 制造商:Lattice Semiconductor Corporation 功能描述:
ISPPAC-POWR1208-01T44E 功能描述:監(jiān)控電路 PROGRAMMABLE PWR SUPPLY CONTR RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開(kāi)關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
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