參數(shù)資料
型號(hào): ISPPAC-POWR1014
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
中文描述: 在系統(tǒng)可編程電源監(jiān)控器,復(fù)位發(fā)生器和排序控制器
文件頁(yè)數(shù): 23/45頁(yè)
文件大小: 999K
代理商: ISPPAC-POWR1014
Lattice Semiconductor
ispPAC-POWR1014/A Data Sheet
23
I
2
C/SMBUS Interface (ispPAC-POWR1014A Only)
I
2
C and SMBus are low-speed serial interface protocols designed to enable communications among a number of
devices on a circuit board. The ispPAC-POWR1014A supports a 7-bit addressing of the I
2
C communications proto-
col, as well as SMBTimeout and SMBAlert features of the SMBus, enabling it to easily integrated into many types
of modern power management systems. Figure 14 shows a typical I
2
C configuration, in which one or more ispPAC-
POWR1014As are slaved to a supervisory microcontroller. SDA is used to carry data signals, while SCL provides a
synchronous clock signal. The SMBAlert line is only present in SMBus systems. The 7-bit I
2
C address of the
POWR1014A is fully programmable through the JTAG port.
Figure 14. ispPAC-POWR1014A in I
2
C/SMBUS System
In both the I
2
C and SMBus protocols, the bus is controlled by a single MASTER device at any given time. This mas-
ter device generates the SCL clock signal and coordinates all data transfers to and from a number of slave devices.
The ispPAC-POWR1014A is configured as a slave device, and cannot independently coordinate data transfers.
Each slave device on a given I
2
C bus is assigned a unique address. The ispPAC-POWR1014A implements the 7-bit
addressing portion of the standard. Any 7-bit address can be assigned to the ispPAC-POWR1014A device by pro-
gramming through JTAG. When selecting a device address, one should note that several addresses are reserved
by the I
2
C and/or SMBus standards, and should not be assigned to ispPAC-POWR1014A devices to assure bus
compatibility. Table 6 lists these reserved addresses.
Table 6. I
2
C/SMBus Reserved Slave Device Addresses
Address
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1xx
0001 000
0001 100
0101 000
0110 111
1100 001
1111 0xx
1111 1xx
R/W bit
0
1
x
x
x
x
x
x
x
x
x
x
x
I
2
C function Description
General Call Address
Start Byte
CBUS Address
Reserved
Reserved
HS-mode master code
N
A
N
A
N
A
N
A
N
A
10-bit addressing
Reserved
SMBus Function
General Call Address
Start Byte
CBUS Address
Reserved
Reserved
HS-mode master code
SMBus Host
SMBus Alert Response Address
Reserved for ACCESS.bus
Reserved for ACCESS.bus
SMBus Device Default Address
10-bit addressing
Reserved
MICROPROCESSOR
(I
C MASTER)
POWR1014A
(I
C SLAVE)
POWR1014A
(I
C SLAVE)
SDA
SDA
SDA
SCL
SCL
SCL
SCL/SMCLK (CLOCK)
SDA/SMDAT (DATA)
SMBALERT
OUT5/
SMBA
OUT5/
SMBA
To Other
I
C
Devices
INTERRUPT
V+
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ISPPAC-POWR1014_08 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
ispPAC-POWR1014-01T48I 功能描述:監(jiān)控電路 Prec. Prog. Pwr Sppl y Seq. Mon. Trim I RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲(典型值):10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
ISPPAC-POWR1014-01TN148I 制造商:Lattice Semiconductor Corporation 功能描述:#WR MGR ISP RESET & SEQ CNTRL 48TQFP
ispPAC-POWR1014-01TN48I 功能描述:監(jiān)控電路 Prec. Prog. Pwr Sppl y Seq. Mon. Trim I RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲(典型值):10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
ispPAC-POWR1014-02T48I 功能描述:監(jiān)控電路 Prec Progm Pwr Sply Seq Mon Trim, IND RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲(典型值):10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel