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參數資料
| 型號： | ISPPAC-POWR1014 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| 中文描述： | 在系統(tǒng)可編程電源監(jiān)控器，復位發(fā)生器和排序控制器 |
| 文件頁數： | 19/45頁 |
| 文件大?。?/td> | 999K |
| 代理商： | ISPPAC-POWR1014 |
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Lattice Semiconductor
ispPAC-POWR1014/A Data Sheet
19
PLD Block
Figure 9 shows the ispPAC-POWR1014/A PLD architecture, which is derived from the Lattice's ispMACH 4000
CPLD. The PLD architecture allows the flexibility in designing various state machines and control functions used for
power supply management. The A
N
D array has 53 inputs and generates 123 product terms. These 123 product
terms are divided into three groups of 41 for each of the generic logic blocks, GLB1, GLB2, and GLB3. Each GLB
is made up of eight macrocells. In total, there are 24 macrocells in the ispPAC-POWR1014/A device. The output
signals of the ispPAC-POWR1014/A device are derived from GLBs as shown in Figure 9. GLB3 generates timer
control.
Figure 9. ispPAC-POWR1014/A PLD Architecture
Macrocell Architecture
The macrocell shown in Figure 10 is the heart of the PLD. The basic macrocell has five product terms that feed the
OR gate and the flip-flop. The flip-flop in each macrocell is independently configured. It can be programmed to
function as a D-Type or T-Type flip-flop. Combinatorial functions are realized by bypassing the flip-flop. The polarity
control and XOR gates provide additional flexibility for logic synthesis. The flip-flop’s clock is driven from the com-
mon PLD clock that is generated by dividing the 8 MHz master clock by 32. The macrocell also supports asynchro-
nous reset and preset functions, derived from either product terms, the global reset input, or the power-on reset
signal. The resources within the macrocells share routing and contain a product term allocation array. The product
term allocation array greatly expands the PLD’s ability to implement complex logical functions by allowing logic to
be shared between adjacent blocks and distributing the product terms to allow for wider decode functions.
AND Array
53 Inp
u
ts
123 PT
Glo
b
al Reset
(Reset
b
pin)
O
u
tp
u
t
Feed
b
ack
24
V
MON[1-10]
20
IN[1:4]
Timer1
Timer2
Timer3
Timer0
Timer Clock
IRP
1
8
PLD Clock
4
4
AGOOD
GLB1
Generic Logic Block
8
Macrocell
41 PT
GLB2
Generic Logic Block
8
Macrocell
41 PT
GLB3
Generic Logic Block
8
Macrocell
41 PT
H
V
OUT[1..2],
OUT[3..
8
]
OUT[9..14]
41
41
41
相關PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-POWR1014-01T48I | In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| ISPPAC-POWR1014-01TN48I | In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| ISPPAC-POWR1014A | In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| ISPPAC-POWR1014A-01T48I | In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| ISPPAC-POWR1014A-01TN48I | In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISPPAC-POWR1014_08 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| ispPAC-POWR1014-01T48I | 功能描述:監(jiān)控電路 Prec. Prog. Pwr Sppl y Seq. Mon. Trim I RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數: 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ISPPAC-POWR1014-01TN148I | 制造商:Lattice Semiconductor Corporation 功能描述:#WR MGR ISP RESET & SEQ CNTRL 48TQFP |
| ispPAC-POWR1014-01TN48I | 功能描述:監(jiān)控電路 Prec. Prog. Pwr Sppl y Seq. Mon. Trim I RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數: 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ispPAC-POWR1014-02T48I | 功能描述:監(jiān)控電路 Prec Progm Pwr Sply Seq Mon Trim, IND RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數: 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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